1.

INTRODUCTION

1.1 PROJECT OVERVIEW

An Arithmetic Logic Unit (ALU) is the heart of a computer's central

processing unit (CPU), responsible for performing mathematical calculations
and logical operations. It's like a mathematical powerhouse inside the
computer, capable of adding, subtracting, multiplying, dividing, and making
decisions like comparing numbers. The ALU plays a crucial role in executing
instructions and processing data, which are the fundamental tasks of any
computer.

A 4-bit Arithmetic Logic Unit (ALU) is a fundamental component of digital

circuits and microprocessors, designed to perform arithmetic and logical
operations on 4-bit binary numbers. In computing, each binary digit (bit) can
represent either a '0' or a '1,' allowing for a total of 16 possible combinations
(2^4) in a 4-bit system. The 4-bit ALU operates on these binary inputs,
executing a wide range of operations, including addition, subtraction, AND,
OR, XOR (exclusive OR), as well as logical shifts and comparisons. It plays a
crucial role in small-scale computing tasks and educational applications,
where it serves as an essential building block for understanding computer
architecture and digital logic.

A 4-bit ALU is designed in VERILOG and implemented on FPGA board.

Implementation of ALU on a FPGA board gives us the necessary data
regarding the hardware testing us the necessary data regarding the hardware
testing of the said circuit. ALU can determine the result of different types of
arithmetic and logical operations performed on any two variables. The ALU
performs the operation based on the code given by the control unit on two
variables otherwise known as operand. the output results from the operation
between the two operands. Designed ALU will perform the following
operations:

Arithmetic operations (Addition, Subtraction, Multiplication and Division)

Logical operations (AND, OR, NOT, NAND, NOR, XOR and XNOR etc.)
Shift operations such as right shift and left sift.
Increment and Decrement operations.

1
1.2 PROJECT OBJECTIVE

The main objective of this project is to design a 4-bit ALU using Xilinx
VIVADO software while focusing on achieving low power consumption. This
design incorporates cutting-edge technologies, including the Manchester carry
chain adder, carry-look-ahead subtractor, Wallace tree multiplier, and
Restoring division. The goal is to implement a comprehensive set of 16
different arithmetic and logical operations. The functions and operations
performed by the ALU with help of selection lines are given below (TABLE
1).

TABLE 1.2.1. ALU OPERATIONS

Selection Lines Function Operation

0000 A BUFFER
0001 A&B AND
0010 A|B OR
0011 ~(A&B) NAND
0100 ~(A|B) NOR
0101 A^B XOR
0110 ~(A^B) XNOR
0111 ~A NOT
1000 A<<B LEFT SHIFT
1001 A>>B RIGHT SHIFT
1010 A+B ADDITION
1011 A-B SBTRACTION
1100 A*B MULTIPLICATION
1101 A/B DIVISION
1110 A+1 INCREMENT BY 1
1111 A-1 DECREMENT BY 1

2
 2. LITERATURE SURVEY

The project entails designing a 4-bit Arithmetic Logic Unit (ALU) with 16
operations implemented on a Field-Programmable Gate Array (FPGA) using
Xilinx Vivado software. Firstly, foundational texts such as "Digital Design" by
Morris Mano and "Computer Organization and Design" by David A. Patterson
and John L. Hennessy offer indispensable insights into ALU design principles,
data path architecture, and control unit intricacies. For the FPGA aspect,
research papers and articles discussing FPGA-based ALU design serve as
crucial guides, shedding light on FPGA toolchain utilization and design
considerations. Furthermore, to attain the goal of low power consumption,
exploring the realm of low-power FPGA design techniques, as detailed in
works like "Low Power FPGA Design Methodologies" by Kaijian Shi and
Kanupriya Gulati, proves indispensable.

For the specific operations to be incorporated into the ALU, extensive research
on each operation is recommended. The Manchester carry chain adder, for
example, can be explored through papers such as "A Low Power Carry Chain
Adder for High-Speed Applications" by Peiman Ghodousi. Similarly, the
study of carry look-ahead subtractors can be enriched by resources like
"Design of High-Performance Carry-Lookahead Adders and Subtractors" by
R. Govindarajan and V. S. Adve. Wallace tree multipliers, as a critical
component, are well-documented in works like "Low-Power High-
Performance Wallace Tree Multiplier" by Reza Rezagholi and Reza
Pourahmadi. For division operations, research on FPGA-friendly division
algorithms is vital, with papers like "Efficient FPGA Implementation of
Division Algorithms" by Jean-Pierre Deschamps providing valuable insights.

Regarding logic operations, textbooks like "Digital Design and Computer

Architecture" by David Money Harris and Sarah L. Harris extensively cover
fundamental logic operations such as AND, OR, NOT, NAND, NOR, XOR,
and XNOR. Buffer design, another crucial aspect, can be explored in texts like
"CMOS Digital Integrated Circuits: Analysis and Design" by Sung-Mo Kang
and Yusuf Leblebici. Shift operations, including right shift and left shift, are
foundational in ALU design and can be found in digital design resources such
as "Digital Logic and Microprocessor Design with VHDL" by Enoch O.
Hwang. Lastly, increment and decrement operations can be studied within the
context of arithmetic operations in digital systems.

3
 START

3. METHODOLOGY

A 4-bit Arithmetic Logic Unit (ALU) with two inputs, A and B, uses a
multiplexer to select and perform various arithmetic and logical
operations. The fig 3.1 explains about the operation of ALU.

Initialize input registers A and B with 4-bit binary numbers

Perform the logical and arithmetic operations on inputs A and B

Read the control input OP to determine the desired Operation

OPCODE

16 x 1 MUX

Output/ Result

Store the result in the output register

Result
 Fig 3.1. FLOW CHART

ADDITION
A[3:0 B[3:0]
] SUBTRACTION

MULTIPLICATION

DIVISION

AND

OR

NAND

NOR
OUTPUT
XOR 16X1 MUX

XNOR

NOT

BUFFER

INCREMENTER

DECREMENTER

RIGHT SHIFT

LEFT SHIFT

S [3:0]

Fig 3.2. BLOCK Diagram

5
 4. HARDWARE AND SOFTWARE REQUIREMENTS

4.1 XILINX VIVADO SOFTWARE

Xilinx Vivado is a cutting-edge integrated development environment (IDE)

designed for digital system design, particularly for field-programmable gate
arrays (FPGAs) and complex programmable logic devices (CPLDs). This
software suite plays a pivotal role in all stages of FPGA development, from
initial design and simulation to synthesis, implementation, and programming.
Vivado offers a user-friendly and highly efficient platform that enables
hardware engineers, FPGA designers, and embedded systems developers to
create and optimize digital designs with ease. Notably, Vivado supports
hardware description languages like VHDL and Verilog, allowing users to
design custom digital circuits and systems. Furthermore, it provides advanced
synthesis and place-and-route tools that help transform these designs into
optimized bitstreams that can be programmed onto FPGAs, ensuring high
performance and efficient resource utilization. Additionally, Vivado offers
powerful debugging and verification features, making it an indispensable tool
for developing complex digital systems and accelerating the creation of
innovative hardware solutions. This software suite continues to be at the
forefront of FPGA development, enabling engineers and researchers to push
the boundaries of digital design and accelerate their projects' time-to-market.

6
 Fig 4.1. Xilinx VIVADO Workspace

4.2 ARTIX-7 FPGA BOARD

The Artix-7 FPGA board is a versatile hardware platform that incorporates

Xilinx's Artix-7 Field-Programmable Gate Array (FPGA) chip. This board is
widely used for educational purposes, prototyping, and small-scale embedded
system development. At its core, the Artix-7 FPGA offers a powerful
reconfigurable logic fabric, making it well-suited for various digital design
and signal processing applications. The board typically features a range of
peripherals and connectors, including GPIO (General-Purpose Input/Output)
pins, memory components (e.g., DDR3 SDRAM), USB ports, Ethernet, and
display interfaces, enabling it to interface with other devices and systems
seamlessly.

Artix-7 FPGAs are known for their cost-effectiveness, making them accessible
for educational institutions and hobbyists while still offering substantial
computational capabilities. This FPGA family is characterized by its balance
between logic capacity, performance, and power efficiency, making it suitable
for a broad spectrum of projects, from small-scale digital signal processing to
real-time control systems.

The Artix-7 FPGA board typically comes with integrated development tools
and software, such as Xilinx Vivado, which simplifies the process of
designing, simulating, synthesizing, and programming the FPGA. These
features, combined with its affordability and flexibility, have made the Artix-7
FPGA board a popular choice for individuals and institutions looking to
explore and implement digital design concepts, develop prototypes, or learn
about FPGA technology.

7
 Fig 4 .2.1 EDGE Artix-7 FPGA board

5. LOGICAL OPERATIONS

5.1 AND gate

An AND gate is a digital logic gate that performs a logical AND operation. It
takes two binary input signals (A and B) and produces a single binary output
based on the following truth table:

TABLE 5.1.1. AND GATE TRUTH TABLE

A B Y(OUTPUT)
0 0 0
0 1 0
1 0 0
1 1 1

The AND gate expression is given by-

Y=A&B

8
(1)
Where ‘&’ is used for AND operation.

SOURCE CODE:

module AND(
input [3:0]a,
input [3:0]b,
output [3:0] y);
assign y = a & b;
endmodule

SCHEMATIC:

Fig 5.1.1. AND gate

5.2 OR gate
An OR gate is a digital logic gate that performs a logical OR operation. It
takes two binary input signals (A and B) and produces a single binary output
based on the truth table:

TABLE 5.2.1. OR GATE TRUTH TABLE

A B Y(OUTPUT)
0 0 0
0 1 1
1 0 1
1 1 1

The OR gate expression is given by-

Y=A|B
(2)
Where ‘|’ is used for OR operation.

SOURCE CODE:

module OR(
input [3:0]a,
input [3:0]b,
output [3:0] y);
assign y = a | b;
endmodule

9
SCHEMATIC:

Fig 5.2.1. OR gate

5.3 NOT gate

A NOT gate, also known as an inverter, is a digital logic gate that performs a
logical NOT operation. Unlike other gates that have multiple inputs, a NOT
gate has only one input and one output. The function of a NOT gate is to
invert or complement the input signal.

TABLE 5.3.1. NOT GATE TRUTH TABLE

A Y
0 1
1 0

The NOT gate expression is given by-

Y= ~A
(3)
Where ‘~’ is used for NOT operation.

SOURCE CODE:

module NOT(
input [3:0]a,
output [3:0] y);
assign y = ~a;
endmodule

SCHEMATIC:

10
 Fig 5.3.1. NOT Gate

5.4 NAND gate

A NAND gate is a digital logic gate that performs the logical AND operation
followed by the logical NOT operation on its inputs. In simpler terms, it
produces the opposite of the AND gate output. A NAND gate has two or more
inputs and one output.

TABLE 5.4. NAND GATE TRUTH TABLE

A B Y(OUTPUT)
0 0 1
0 1 1
1 0 1
1 1 0

The NAND gate expression is given by-

Y= ~(A&B)
(4)
Where ‘~’ is used for NOT operation and ‘&’ is used for AND operation.

SOURCE CODE:

module NAND(
input [3:0]a,
input [3:0]b,
output [3:0] y);
assign y = ~(a & b);
endmodule

SCHEMATIC:

Fig 5.4.1. NAND Gate

5.5 NOR Gate

A NOR gate is a digital logic gate that performs the logical OR operation
followed by the logical NOT operation on its inputs. In simpler terms, it
produces the opposite of the OR gate output. A NOR gate has two or more
inputs and one output.

TABLE 5.5.1. NOR GATE TRUTH TABLE

A B Y(OUTPUT)

11
 0 0 1
0 1 0
1 0 0
1 1 0

The NOR gate expression is given by-

Y= ~(A|B)
(5)
Where ‘~’ is used for NOT operation and ‘|’ is used for OR operation.

SOURCE CODE:
module NOR(
input [3:0]a,
input [3:0]b,
output [3:0] y);
assign y = ~(a |b);
endmodule

SCHEMATIC:

Fig 5.5.1. NOR Gate

5.6 XOR Gate

An XOR gate (exclusive OR gate) is a digital logic gate that performs the
logical exclusive OR operation on its inputs. An XOR gate has two inputs and
one output. The output of an XOR gate is true (logic 1) if the number of true
inputs is odd.

TABLE 5.6.1. XOR GATE TRUTH TABLE

A B Y(OUTPUT)
0 0 0
0 1 1
1 0 1
1 1 0

The XOR gate expression is given by-

Y=A^B
(6)
Where ‘^’ is used for XOR operation.

SOURCE CODE:

12
module EXOR(
input [3:0]a,
input [3:0]b,
output [3:0] y);
assign y = (a ^ b);
endmodule

SCHEMATIC:

Fig 5.6.1. XOR Gate

5.7 XNOR Gate

An XNOR gate (exclusive NOR gate) is a digital logic gate that performs the
logical exclusive NOR operation on its inputs. An XNOR gate is also known
as an equivalence gate because it produces a true output (logic 1) when the
number of true inputs is even, making it the logical complement of the XOR
(exclusive OR) gate.

TABLE 5.7.1. XNOR GATE TRUTH TABLE

A B Y(OUTPUT)
0 0 1
0 1 0
1 0 0
1 1 1

The XNOR gate expression is given by-

Y= ~(A^B)
(7)
Where ‘~’ is used for NOT operation and ‘^’ is used for XOR operation.

SOURCE CODE:

module XNOR(
input [3:0]a,
input [3:0]b,
output [3:0] y);
assign y = ~(a ^ b);
endmodule
SCHEMATIC:

13
 Fig 5.7.1. XNOR Gate

5.8 BUFFER Gate

A BUFFER gate, also referred to as a unity-gain buffer or simply a buffer, is a

basic digital logic gate with one input and one output. The purpose of a
BUFFER gate is to pass its input signal to the output without any change in
logic level or voltage level.

TABLE 5.8.1. BUFFER GATE TRUTH TABLE

A Y(OUTPUT)
0 0
1 1

The BUFFER gate expression is given by-

Y=A
(8)

SOURCE CODE:

module buffer(
input [3:0]a,
output [3:0] y);
assign y = a;
endmodule

SCHEMATIC:

Fig 5.8.1. BUFFER Gate

6. SHIFT OPERATORS
The Shift operators are used to perform shifting operations. Shift operator

14
provides the output by shifting the operands either towards the left or right
shift according to the number of bit specified by the user. The left shift
operation is performed by shifting the bits towards left using the left shift
operator ‘<<’. Similarly, the right shift operator ‘>>’ shifts the bits towards
right.

LEFT SHIFT:

SOURCE CODE:

module carry(
input [3:0] A,
input [3:0] B, // 4-bit input A
output [3:0] y);
assign y=A<<B;
endmodule

SCHEMATIC:

Fig 6.1 Left Shift Operator

RIGHT SHIFT:

SOURCE CODE:

module carry(
input [3:0] A,
input [3:0] B, // 4-bit input A
output [3:0] y);
assign y=A>>B;
endmodule

15
SCHEMATIC:

Fig 6.2 Right Shift Operator

7. ARITHETIC OPERATIONS

7.1 MANCHESTER CARRY CHAIN ADDER

The Manchester Carry Chain Adder is a type of adder circuit used in digital
electronics and arithmetic units for adding binary numbers. It's a carry-
propagate adder that can efficiently propagate carry bits across multiple stages
of the adder, which makes it suitable for high-speed arithmetic operations.
The sum and carry expressions are given by-
Sum = A ^ B ^ Cin
(9)
Where ‘^’ is used for XOR operation.
Cout = (A&B)|(B & Cin)|(Cin & A)
(10)
Where A, B, Cin are the inputs, Sum and Cout are the outputs, ‘|’ used for OR
operation and ‘&’ used for AND operation.

SOURCE CODE:
module ManchesterCarryChainAdder (
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
output [3:0] Sum, // 4-bit sum output
output Cout // Carry out
);

wire [3:0] G; // Generate signals

wire [3:0] P; // Propagate signals
wire [3:0] C; // Carry signals

16
 // Generate and Propagate signals
assign G = A & B;
assign P = A ^ B;
assign C[0] = 0; // Initialize the first carry bit to 0
// Generate Carry Chain
genvar i;
generate
for (i = 1; i < 4; i = i + 1) begin
assign C[i] = G[i-1] | (P[i-1] & C[i-1]);
end
endgenerate
// Sum Bits
assign Sum = A ^ B ^ C;
// Carry out
assign Cout = C[3];
endmodule

SCHEMATIC:

Fig 7.1.1. Manchester carry chain adder

7.2 CARRY LOOK AHEAD SUBTRACTOR

A Carry Look-Ahead Subtractor (CLA Subtractor) is a digital circuit used to
perform binary subtraction. It's an advanced subtractor design that utilizes
carry look-ahead logic to accelerate the subtraction process by computing the
borrow (carry-in) signals for each stage of subtraction in parallel, rather than
in a serial fashion as in a ripple-carry subtractor.
The difference and Borrow expressions are given by-
Diff = A ^ B ^ Borrow in
(11)
Where ‘^’ is used for XOR operation.
Borrow out = (~A) & (B ^ Borrow in) | (B & Borrow in)
(12)

Where A, B, Borrow in are the inputs, Diff and Borrow out are the outputs, ‘~’

17
used for NOT operation, ‘&’ used for AND operation and ‘|’ used for OR
operation.

SOURCE CODE:

module carry(
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
output [3:0] Diff, // 4-bit difference output
output BorrowOut // Borrow out
);
wire [3:0] G; // Generate signals
wire [3:0] P; // Propagate signals
wire [3:0] C; // Carry signals
// Generate and Propagate signals
assign G = A & ~B;
assign P = A ^ B;
assign C[0] = A[0] & ~B[0]; // Initialize the first carry bit to G0
assign BorrowOut = C[3]; // Borrow out is the MSB carry bit
// Generate Carry Look-Ahead
generate
genvar i;
for (i = 1; i < 4; i = i + 1) begin
assign C[i] = G[i-1] | (P[i-1] & C[i-1]);
end
endgenerate
// Difference bits
assign Diff = A - B;
endmodule
SCHEMATIC:

Fig 7.2.1. Carry look Ahead Subtractor

7.3 WALLACE TREE MULTIPLIER

A Wallace Tree Multiplier, also known as a Wallace Tree or Modified Booth
Wallace Tree Multiplier, is a hardware circuit used to perform fast binary
multiplication of two binary numbers. It's a type of multiplier architecture that
leverages parallelism to speed up the multiplication process, making it well-
suited for high-performance computing systems and digital signal processing
applications.

18
The Boolean Expressions for multiplication is given by-
Y= A*B
(13)
Where A, B are inputs, Y is the output and ‘*’ denotes multiplication operator.

SOURCE CODE:
module WallaceTreeMultiplier(
input [3:0]A,
input [3:0]B,
output [7:0]prod
);
reg [3:0]PP1,PP2,PP3,PP4;
wire HAC1,HAC2,HAC3,HAC4;
wire HAS1,HAS2,HAS3,HAS4;
wire FAC1,FAC2,FAC3,FAC4,FAC5,FAC6,FAC7,FAC8;
wire FAS1,FAS2,FAS3,FAS4,FAS5,FAS6,FAS7,FAS8;
always@(*) begin
PP1={A[3]&&B[0],A[2]&&B[0],A[1]&&B[0],A[0]&&B[0]};
PP2={A[3]&&B[1],A[2]&&B[1],A[1]&&B[1],A[0]&&B[1]};
PP3={A[3]&&B[2],A[2]&&B[2],A[1]&&B[2],A[0]&&B[2]};
PP4={A[3]&&B[3],A[2]&&B[3],A[1]&&B[3],A[0]&&B[3]};
end

//stage 1
HA h1 (PP1[2],PP2[1],HAS1,HAC1);
FA f1 (PP1[3],PP2[2],PP3[1],FAS1,FAC1);
FA f2 (PP2[3],PP3[2],PP4[1],FAS2,FAC2);
//stage 2
HA h2 (FAS1,PP4[0],HAS2,HAC2);
HA h3 (FAS2,FAC1,HAS3,HAC3);
FA f3 (PP3[3],PP4[2],FAC2,FAS3,FAC3);
//stage 3
HA h4 (PP1[1],PP2[0],HAS4,HAC4);
FA f4 (HAS1,PP3[0],HAC4,FAS4,FAC4);
FA f5 (HAS2,HAC1,FAC4,FAS5,FAC5);
FA f6 (HAS3,HAC2,FAC5,FAS6,FAC6);
FA f7 (FAS3,HAC3,FAC6,FAS7,FAC7);
FA f8 (PP4[3],FAC3,FAC7,FAS8,FAC8);

assign prod= {FAC8,FAS8,FAS7,FAS6,FAS5,FAS4,HAS4,PP1[0]};

endmodule
//HALF ADDER DECLARATION
module HA(A,B,sum,carry);
input A,B;
output sum,carry;
assign sum= A^B;
assign carry= A&&B;
endmodule
//FULL ADDER DECLARATION
module FA(A,B,Cin,sum, carry);

19
 input A,B,Cin;
output sum,carry;
assign sum= A^B^Cin;
assign carry= (A&&B)||(Cin&&(A^B));
endmodule

SCHEMATIC:

Fig 7.3.1. Wallace tree multiplier

7.4 RESTORING DIVISION

Restoring division is a method of binary integer division used in digital
computing and microprocessor architectures. It's one of the classic techniques
for performing division operations on binary numbers. In restoring division,
both the quotient and remainder are computed as binary numbers.

SOURCE CODE:

module division(A,B,Q);
input [3:0] A;
input [3:0] B;
output [3:0] Q;
//internal variables
reg [3:0] Q = 0;
reg [3:0] a1,b1;
reg [3:0] p1;
integer i;
always@ (A or B)
begin
//initialize the variables.
a1 = A;
b1 = B;
p1= 0;
for(i=0;i < 4;i=i+1) begin //start the for loop

20
 p1 = {p1[4-2:0],a1[3]};
a1[3:1] = a1[2:0];
p1 = p1-b1;
if(p1[3] == 1) begin
a1[0] = 0;
p1 = p1 + b1; end
else
a1[0] = 1;
end
Q = a1;
end
endmodule

SCHEMATIC:

Fig 7.4. Restoring Division

8. INCREMENT AND DECREMENT OPERATOR

The Increment operator ‘++’ is used to add 1 to the operand and the decrement
operator ‘--’ is used to subtract from the operand. These are the unary
operators which needs only one operand to execute its operation. These are
commonly used to add or subtract ‘1’ to the given variable or operand
respectively.

21
 1. RTL SCHEMATIC OF 4-BIT ALU

RTL (Register Transfer Logic) provides the complete idea about the internal
structure of the ALU designed. With the help of RTL schematic anyone can
understood the internal connection of the ALU as per the written code. It
transfers the given code into gate level design by specifying all registers and
the internal connection in between them. It reduces the complexity and
provides better understanding and verification of the designed ALU.

Fig 9.1.1. RTL schematic of 4-bit ALU

22
 2. SIMULATION

10.1 By behavioral simulation for selection line equal to “1010”, It performs

Manchester Carry Chain Adder operation, i.e., A+B and gives the following
results.

Fig 10.1.1. Simulation result for Addition operation

10.2 When the selection line is equal to “1011”, It performs Carry Look
Ahead Subtractor operation, i.e., A-B and gives the following results.

Fig 10.2.1. Simulation Result for Subtraction operation

10.3 When the selection line is equal to “1100”, It performs Wallace Tree
Multiplication operation, i.e., A*B and gives the following results.

Fig 10.3.1. Simulation Result for Multiplication operation

10.4 When the selection line is equal to “1101”, It performs Restoring

Division operation, i.e., A/B and gives the following results.

23
 Fig 10.4.1. Simulation Result foe Division Operation

3. POWER CONSUMPTION REPORT

The power consumption of the design is improved. In this project we used

advanced versions of arithmetic circuits such as Manchester carry chain
adder, Carry look ahead subtractor and Wallace tree multiplier etc.

Fig 11.1 Power Consumption Report

4. DISCUSSION & CONCLUSION

ALU is the main elemental part of processor, and updating an ALU, in

sense of power reduction, can enhance the capability of processor. This
can be attained from reduction in power consumption and FPGA resource
consumption. As we seen from the simulation result and power report that
our model is working as per the specifications. As we can see from the
synthesis report that our design has low power consumption as compared
to base paper design. The code was written using Xilinx VIVADO tool
and ALU was successfully designed and implemented using verify logic
hardware description language and Artix-7 Field Programmable Gate
Array.

24
REFERENCES:

[1]Amrit Kumar Panigrahi; Sasmita Patra; Muskan Agrawal; Subhasis

Satapathy; Design and Implementation of a high speed 4bit ALU using
BASYS3 FPGA Board. 2019 Innovations in Power and Advanced Computing
Technologies (i-PACT) Year: 2019 | Conference Paper | Publisher: IEEE.
[2] Nidhi Gaur; Anu Mehra; Pradeep Kumar; Enhanced AES Architecture
using Extended Set ALU at 28nm FPGA. 2018 5th International Conference
on Signal Processing and Integrated Networks (SPIN) Year: 2018 |
Conference Paper | Publisher: IEEE
[3] Design of a 4 Bit Arithmetic & Logic Unit, Evaluation of Its Performance
Metrics & its Implementation in a Processor 2020 International Conference
for Emerging Technology (INCET) Belgaum, India. Jun 5-7, 2020

25