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DFT Interview Notes

The document outlines key concepts of Design for Testability (DFT), emphasizing its role in enhancing the testability of digital designs through controllability and observability. It details various testing methodologies, scan design concepts, and techniques such as scan insertion, scan reordering, and clock skew fixes. DFT is implemented after synthesis and before place and route in the ASIC design flow.

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10 views1 page

DFT Interview Notes

The document outlines key concepts of Design for Testability (DFT), emphasizing its role in enhancing the testability of digital designs through controllability and observability. It details various testing methodologies, scan design concepts, and techniques such as scan insertion, scan reordering, and clock skew fixes. DFT is implemented after synthesis and before place and route in the ASIC design flow.

Uploaded by

venkyvenkatesheleven
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DFT Interview Questions – Organized

Notes
1. Basics of DFT
• DFT (Design for Testability) is used to improve the testability of digital designs.

• It provides controllability and observability to internal nodes.

• Functional Testing: Tests based on functionality (slow, high pattern count).

• Structural Testing: Targets manufacturing defects (faster, ATPG based).

• Full Scan: All FFs are scan FFs → High coverage, high test time.

• Partial Scan: Some FFs are scan FFs → Lower coverage, faster test.

• DFT is inserted after synthesis, before P&R in the ASIC flow.

2. Scan Design Concepts


• Scan Insertion adds multiplexers to flip-flops to create a scan chain.

• Scan Types: Muxed Scan, Clocked Scan, LSSD.

• Scan Operation: Shift-In → Capture → Shift-Out.

• Scan Reordering: Reorders FFs to reduce routing.

• Scan Stitching: Connects scan FFs into chains.

• Lockup Latches: Fix hold violations and clock skew between domains.

• Clock Skew Fix: Use same clock domain or insert lockup latches.

• Chain Balancing: Even distribution of FFs across scan chains to minimize shift time.

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