Tutorial-7
Tarush Mehta, Murali
March 29, 2024
1. Calculate the total count of address lines and input-output lines from a RAM with the following
specifications. Also give the number of bytes stored in each memory.
(a) 1K x 16
(b) 512K x 32
(c) 8G x 64
2. (a) How many 32K * 8 RAM chips are needed to provide a memory capacity of 256K bytes? (b)
How many lines of the address must be used to access 256K bytes? How many of these lines are
connected to the address inputs of all chips? (c) How many lines must be decoded for the chip select
inputs? Specify the size of the decoder.
3. A DRAM chip uses two-dimensional address multiplexing. It has 13 common address pins in both
rows and columns, with data size of 1 byte. What is the capacity of the memory?
4. A 16K * 4 memory uses coincident decoding by splitting the internal decoder into X -selection and
Y -selection. (a) What is the size of each decoder, and how many AND gates are required for decoding
the address? (b) Determine the X and Y selection lines that are enabled when the input address is
the binary equivalent of 6,000.
5. Draw the timing diagrams (illustrating the Clock, Memory address, Memory enable, Read- /Write,
Data input) for both the Read and the Write cycles for a CPU with clock frequency 2 GHz, and a
RAM with a write cycle and read cycle both within 1.8 ns.
6. Construct the 16*4 ROM with the required number of OR gates and a decoder and mark the
crosspoints according to the Boolean functions given below
P
(a) D3 = (0, 2, 3, 12)
P
(b) D2 = (0, 3, 10, 11, 14)
P
(c) D1 = (1, 2, 4, 6)
P
(d) D0 = (4, 5, 7, 8, 9, 13)
7. ROM can be used to store the function y = x2 + 3, where the input address supplies the value for
x, and the value of the output data is y. Derive the ROM programming table for the combinational
circuit that implements this function and minimize the number of product terms.
8. Using 32 * 8 ROM chips with an enable input, give the number of these 32*8 chips required to
implement the following and construct them.
(a) 64*8 ROM
(b) 256*8 ROM
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9. Given below are the POS equations of the data output lines of an 8 x 4 ROM. Now construct the
ROM using these Boolean equations, a suitable decoder and OR gates.
(a) D0(A, B, C) = (A + B) A
(b) D1(A, B, C) = (A + B’ + C)(A’ + B)
(c) D2(A, B, C) = B(A’ + B + C’)
(d) D3(A, B, C) = (B + C)(A’ + C’)
10. A 16 x 4 ROM is implemented using a 4 to 16 decoder and some output buffers as shown in the
figure-1. The inputs of the decoder are connected to the outputs of a MOD-16 counter with a negative
edge triggered clock which have a frequency of 100 kHz. Ignore ROM delay times. Assume that the
counter starts at 0000.
(a) Find the data stored at every address location of the ROM
(b) What is data present at the outputs of the ROM at 80 microseconds and 103 microseconds
(Assume clock is given at t=0)
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Practice Questions
11. How many data outputs and address inputs are needed for the following?
(a) 1024b x 4b ROM
(b) 128b x 8b ROM
(c) 4096b x 16b ROM
(d) 1024 B x 4B ROM
12. Write the truth table for a 8* P
P 4 ROM that implements the Boolean P functions :D3 (w, x, y, z) =
P m(0, 1, 3, 4, 6), D2 (w, x, y, z) = m(1, 2, 4, 7), D1 (w, x, y, z) = m(0, 2, 3, 5), D0 (w, x, y, z) =
m(5, 7).Considering now the ROM as a memory, specify the memory contents at addresses 2 and 6.
13. Another ROM application is the generation of timing and control signals. The figure in the next
page shows a 16 × 8 ROM with its address inputs driven by a MOD-16 counter so that the ROM
addresses are incremented with each input pulses. Assume that the ROM is programmed as in Figure
2, and sketch the waveforms at ROM outputs D0, D1, D4, D7 as the pulses are applied. Ignore ROM
delay times. Assume that the counter starts at 0000.
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14. Draw a block diagram that shows how a ROM and D flip-flops could be connected to realize table
below. Specify the truth table for the ROM using a straight binary state assignment.
15. ROM chips with the following size(s) and number of chip-select lines, operates from a 5-V power
supply. How many pins are needed for the integrated circuit package? Draw a block diagram, and
label all input and output terminals in the ROM.
(a) 2048 x 8; 2 chip-select lines
(b) 8192 x 16; 3 chip-select lines
16. A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number
of rows is equal to the number of columns). What is the minimum number of address lines needed for
the row decoder?
17. In his electronics lab class, Raj is tasked with building an 8 x 8 RAM. The lab has no 1-bit memory
cells available to connect together. However, fortunately, the lab has several 4 x 4 RAMs lying around.
Help Raj construct an 8 x 8 RAM using the 4 x 4 RAMs as building blocks. (Enclose each 4 x 4 RAM
in a block diagram of its own, showing its inputs and outputs.) The effective 8 x 8 RAM must have all
the functionality that the 4 x 4 RAM has - such as reading/writing an entire word, memory enable,
read/write, etc.
