CLOCK TREE SYNTHESIS:
Prerequisites for Clock Tree Synthesis
Before performing clock tree synthesis tool identifies the clock sources with
create_clock ,create_generated_clocks
Before Performing Clock tree synthesis verify the placement is legal or not
Check_legality –verbose it checks the congestion .congestion is high it leads
timing issues in later stages.
Verifying the Clock Trees
check_clock_trees -clocks [get_clocks CLK]
command checks for the following issues:
• Clock (master or generated) with no sinks
• Loops in the clock network
• Multiple clocks reach the same register because of overlapping clocks, but multiple clocks-per-
register propagation is not enabled
• Ignored clock tree exceptions
• Stop pin or float pin defined on an output pin
• Buffers with multiple timing arcs used in clock tree references
• Situations that cause an empty buffer list
Setting Clock Tree Design Rule Constraints
set_max_transition 0.20 -clock_path [get_clocks CLK]
set_max_capacitance 0.6pf -clock_path [get_clocks CLK]
Specifying the Clock Tree References
The buffer and inverter cells that can be used to build a clock tree and the
reference cells of the preexisting gates of the clock tree are referred to as clock
tree references.
set_lib_cell_purpose -include cts
The library cells in the reference list do not have a dont_touch attribute If
library cells have the dont_touch attribute set on them, they are not used by
clock tree synthesis even if you specify them as clock tree references .
set cts_cells list_of_cells
icc2_shell> set_lib_cell_purpose -exclude cts [get_lib_cells]
icc2_shell> set_lib_cell_purpose -include none [get_lib_cells $cts_cells]
icc2_shell> set_lib_cell_purpose -include cts [get_lib_cells $cts_cells]
Therefore, you must manually specify the buffers and inverters to use for
clock tree synthesis, as shown in the following example:
icc2_shell> set_lib_cell_purpose -include cts \ {tech_lib/clk_buf*
tech_lib/clk_inv*}
icc2_shell> derive_clock_cell_references
icc2_shell> synthesize_clock_trees
Restricting the Target Libraries Used
You can restrict the libraries used during clock tree synthesis for the top
level or a lower level of the logical hierarchy of a design
icc2_shell> set_lib_cell_purpose -include cts \ {HVT_lib/buf1 HVT_lib/buf2
LVT_lib/buf1 LVT_lib/buf2}
this command include cells for CTS for specific library
icc2_shell> set_target_library_subset -clock {LVT_lib} \-objects
[TOP/TSK_BLK]
this commands set the target library as LVT_Lib for lower level Block
TOP/TSK_BLK
icc2_shell> set_app_options \ -name
opt.common.enable_target_library_subset_opt -value 1
Setting Skew and Latency Targets for low frequency designs. Decrease
the ,power ,area,run time of the design
set_clock_tree_options –target_skew & -target_latency
