CLOCK TREE SYNTHESIS:
Inputs of CTS:
CLOCK SPEC
NETLIST
UPF
LEF and TEC files
.lib
MCMM
CHECKS:
Placement is completed without congestion
Power and ground nets are Prerouted
Minimum timing
High fanout synthesis
Prerequisites for Clock Tree Synthesis
Before performing clock tree synthesis tool identifies the clock sources with
create_clock ,create_generated_clocks
Before Performing Clock tree synthesis verify the placement is legal or not
Check_legality –verbose it checks the congestion .congestion is high it leads
timing issues in later stages.
Verifying the Clock Trees
check_clock_trees -clocks [get_clocks CLK]
command checks for the following issues:
• Clock (master or generated) with no sinks
• Loops in the clock network
• Multiple clocks reach the same register because of overlapping clocks, but multiple clocks-per-
register propagation is not enabled
• Ignored clock tree exceptions
• Stop pin or float pin defined on an output pin
• Buffers with multiple timing arcs used in clock tree references
• Situations that cause an empty buffer list
Identifing the clock roots by create_clock command
set_driving_cell -lib_cell mylib/CLKBUF [get_ports CLK1 ]
it is used to specify the driving cell to the if the root is a CLK port to meet the
DRVs
If the clock root is an input port with an I/O pad cell, you must accurately
specify the input transition time of the input port.
set_input_transition -rise 0.3 [get_ports CLK1]
set_input_transition -fall 0.2 [get_ports CLK1]
Setting Clock Tree Design Rule Constraints
set_max_transition 0.20 -clock_path [get_clocks CLK]
set_max_capacitance 0.6pf -clock_path [get_clocks CLK]
Tool identifies the clock endpoints as sink pins and
ignore pins
During CTS sink pins are used for calculations and optimizations and design
rule constraints,
but ignore pins are not used for skew balncing and optimization only for
meeting the Design rule constraints
icc2_shell> set_clock_balance_points -clock [get_clocks CLK] \-
consider_for_balancing false -balance_points [get_pins U2/A]
# user defined explicit ignore pin
Setting Don’t Touch Settings on clock
network
To set a don't touch setting on a clock tree, use the
set_dont_touch_network command
icc2_shell> set_dont_touch_network -clock_only [get_pins
pin_name]
set_dont_touch [get_cells cell_name] true #sets don’t touch attribute
on cells to prevent CTS optimizatin
set_dont_touch [get_nets -segments net_name] true ##sets don’t
touch attribute on nets to prevent CTS optimization
Specifying the Clock Tree References
The buffer and inverter cells that can be used to build a clock tree and the
reference cells of the preexisting gates of the clock tree are referred to as clock
tree references.
set_lib_cell_purpose -include cts
The library cells in the reference list do not have a dont_touch attribute If
library cells have the dont_touch attribute set on them, they are not used by
clock tree synthesis even if you specify them as clock tree references .
set cts_cells list_of_cells
icc2_shell> set_lib_cell_purpose -exclude cts [get_lib_cells]
icc2_shell> set_lib_cell_purpose -include none [get_lib_cells $cts_cells]
icc2_shell> set_lib_cell_purpose -include cts [get_lib_cells $cts_cells]
Therefore, you must manually specify the buffers and inverters to use for
clock tree synthesis, as shown in the following example:
icc2_shell> set_lib_cell_purpose -include cts \ {tech_lib/clk_buf*
tech_lib/clk_inv*}
icc2_shell> derive_clock_cell_references
icc2_shell> synthesize_clock_trees
Restricting the Target Libraries Used
You can restrict the libraries used during clock tree synthesis for the top
level or a lower level of the logical hierarchy of a design
icc2_shell> set_lib_cell_purpose -include cts \ {HVT_lib/buf1 HVT_lib/buf2
LVT_lib/buf1 LVT_lib/buf2}
this command include cells for CTS for specific library
icc2_shell> set_target_library_subset -clock {LVT_lib} \-objects
[TOP/TSK_BLK]
this commands set the target library as LVT_Lib for lower level Block
TOP/TSK_BLK
icc2_shell> set_app_options \ -name
opt.common.enable_target_library_subset_opt -value 1
Setting Skew and Latency Targets for low frequency designs. Decrease
the ,power ,area,run time of the design
set_clock_tree_options –target_skew & -target_latency
