Clock Tree Synthesis
Learning Objectives
• In this module you will understand what is clock tree synthesis and
its
importance in the physical design flow.
• Clock tree specifications, clock tree methodologies, concept of global
and local skew, etc are discussed.
Learning Plan
• Introduction to CTS < Exceptions
« Clock Distribution in A Block < Stop pins
< CTS in ASIC Flow - Stages « Non-Stop
Pins
• CTS Specifications « Float Pins
< Cells to use in CTS < Exclude Pins
« Target Skew, Target • cTS QoR
Latency, Max Transition
< QoR
Target Summary
« Clock Routing Rules « Clock
Glitter
Learning Plan
• Clock Uncertainty • CTS Distribution Methodologies
< Setup with « H-tree
Slack(reg2reg) « Clock Mesh
Uncertainty
« Hold Slack(reg2reg) with
Uncertainty
• CTS & Opt-Quality Ghecks
< CTS & Opt — Care about
< CTS Distribution
Methodologies
Physical Design Flow Diagram
Design Import
Sign —Off
Physical Verification
Sanity Check
Power EM & IR
Floorplanning and Power Analysis
Planning
LEC extraction
&Timing analysis
Pre-Place, Place and Opt
All
ECO
No Clean
Route Opt & Design Finishing Yes
Tape out
6
Clock Tree Synthesis
Branche FF1
• Building clock tree from s
clock to
port the all- pins Leaf
FF2
clock sequential of Trunk
cells. FF3
• •Goals of CTSClock reaches all
Efficient
Clock Pin FF4
the (transition time, min
flops
pulse width)
FF5
• Minimize Clock Skew
• Minimize Clock latency FF6
Clock Tree Synthesis
Branche FF1
• Before CTS the clock is treated s
to be ideal. After CTS the clock FF2
Leaf
is said to be propagated clock. Trunk
• Clock tree balancing is done FF3
using buffers and inverters Clock Pin FF4
FF5
FF6
Clock Distribution in A Block
Branc
Root Leaf
Trunk/Top
Branc
h
CTS in ASIC Flow - Stages
Placement and Opt
Clock Tracing
Clock Tree Building
CTS Spec
Clock Tree Balancing
Clock Tree Routing
CTS QOR
Post CTS—Opt
Post—CTS STA
CTS Spec
Cells to use in CTS
Target Skew
-> Target Latency
Max Transition Target
Basic — Clock Routing Rules
-¥
L
Type of Clock Tree
Balanced Clock
CTS Spec
Tree, H-Tree, Clock
Mesh,
Clock grouping
Stop pin
Exceptions Float pin
Nonstop pin
Exclude pin
CTS Spec-Cells to use in CTS
Cells to use in CTS
• Clock Cells-Inverters Buffers:
/ Target Skew
Target Latency
Equal rise and fall times. Max Transition Targetq
•Single
LVT: VT:
Lesser
LessDelay
Variations Basic
Clock Routing Rules
between Different PVT.
• Mid Drive Strength Type of Clock Tree
•Low Drive strength cells are CTS Balanced Clock Tree,
Spec H-Tree, Clock Mesh, ,
not preferred because of higher
Clock grouping
delay,
Stop pin
more variations. Exceptions Float pin
•High Drive Strength cells are Nonstop pin
Exclude pin
not preferred because of
power density
CTS Spec Target Skew,
Cells to use in CTS
• Target skew: CTS will
the clock tree s u c h t ha t Target Skew
Target Latency
achievesit the given target Max Transition Target
skew value. Basic
• Target latency: CTS will Clock Routing Rules
the clock tree such that it
build
Type of Clock Tree
achieves the given target latencyCTS Balanced Clock Tree,
Spec H-Tree, Clock Mesh, ,
value.
• Max
build the clock tree
transition suchCTS
target: thatwill Clock grouping
Stop pin
the transition time on any clock Exceptions Float pin
net is less than the given max Nonstop pin
transition target. Exclude pin
CTS Spec - Clock Routing Rules
• Metal layers to be used for CTS
• Width and spacing of metal
Signal Routing-Single Width Single Space
layers
• Shielding
• Metal Layers : Top 2 metal 2S t
layers below the power mesh,
• (low res i sta n ce 3 improves
Double Avoid latency)
EM, low Clock Routing-Double Width double Space
width (faster, improves
resistance
• latency)
Double spacing : Avoid crosstalk
• Shielding grid is also
Vss
with
used to avoid crosstalk Clock Routing-with shielding
CTS Spec - Exceptions
Cells to use in CTS
• By default, CTS Balances Target Skew
the - Target Latency
> Max Transition Target
latency of all sink flops.
Basic
• This Clock Routing Rules
altered default behavior can +
by defining exceptions
be t y p e of Clock Tree
like float pin, exclude pin, etc... Q Balanced Clock Tree,
TS ->
Spe H-Tree, Clock Mesh,
c
Clock grouping
Stop pin
Exceptions Float pin
Nonstop pin
Exclude pin
1
6
CTS Spec - Stop pins
• Stop pins are the endpoints of Stop Pin
the clock tree that are used for FF
delay balancing.
FF
• During clock tree
the uses synthesis, stop CLK Sub Module
calculations
tool and optimizations
for both design rule
pinsconstraints
in
and clock tree timing (skew
and insertion delay).
CTS Spec - Non-Stop Pins
• Nonstop pins are pins that
Non-Stop Pin Stop Pin
would normally be considered
FF
endpoints of the clock tree 3 but
instead the tool traces through FF
them to find the clock tree
endpoints.
• The clock pins IGG Sub Module
* LK
of cell)
(Integrated
are nonstop Clock
Gating
pins. sequential
• The clock generated
cells driving pins clocks
areofimplicit nonstop pins.
IS
CTS Spec - Float Pins
• Float pins are clock pins
that have special insertion FF
delay requirements.
FF
• The tool adds the float pin
delay
(positive or negative) CLK Sub Module
to the calculated insertion
Float Pin
delay up to this pin.
CTS Spec - Exclude Pins
• Exclude pins are clock tree
endpoints that are excluded FF
from clock tree timing FF
calculations and optimizations.
CLK
• The tool uses exclude pins Sub Module
only in calculations and Float Pin
optimizations for design rule
constraints.
Exclude Pin
CTS Specs Exceptions
• The tool implicitly identifies stop pins ,non-stop pins, exclude pin etc..
• Clock tree exceptions are user-defined changes to the default
endpoints derived by the tool.
• For e x am pl e 3 the clock pin identified as a stop pin by the tool can
be changed to exclude pin by defining clock exception on
the pin
Local Skew vs Global Skew
• Global Skew: The skew between any two flops irrespective of
whether
they are interacting or not.
• Local Skew : The skew between two interacting flops
UFF0 UFF1 UFF2
CLK CLK CLK
2.
1ns
CLK
Local Skew =0.6; Global skew = 1.
1
CTS QoR
• Global skew
• Local skew
• Insertion delay/Latency
• Max clock transition violations
• Number of levels
• Number of Clock cells added
QoR Summary
1cc2 shet1> report clock qor
==== Sumna ry Report1ng for Corner fast ====
Sunma ry Table for Corner fast
Clock / Att rs S1nks Levels Clock Clock Clock Hax Global Trans DRC Cap DRC ¥I1re
Skew Group Repeater Repeater Stdcet1 Latency Skex Count Count Length
Count Area Area
#dd Hode: func, Scena r1o: func fast
clock H,D 723 9 32 11 . 81 4I? . 80 e. 56 0.28 0 e 3136.69
All Clocks 723 9 32 11 . 81 4I? . 80 e. 56 0.28 0 e 3136.69
¥/a rn1ng: Please use - la r g e s t / - s m a lle s t / - aft sw1tches w1th - show verbose paths / - show to r e p o r t t h e c l o c k paths . (CTS -
paths 956)
==== Sumna ry Report1ng for Corner stow ====
Sunma ry Table for Corner stow
Clock / Att rs S1nks Levels Clock Clock Clock Nax Global Trans DRC Cap DRC ¥I1re
Skew Group Repeater Repeater Stdcet1 Latency Skex Count Count Length
Count Area Area
#dd Hode: func, Scena r1o: func stow
clock H,D 723 9 32 11 . 81 4I? . 80 e. 56 0.28 0 3 3136. 69
All Clocks 723 9 32 11 . 81 4I? . 80 e. 56 0.28 0 3 3136. 69
Clock Tree S ynt hesi s 2
5
Clock Jitter
• Clock Jitter a is deviation of
clock edge from its ideal
location
• Clock source (PLL) Glitter.
• Clock tree introduced Ideal clock edge
Glitter. jitter
Ideal clock edge
jitter
Clock Uncertainty
• Clock Uncertainty: Dxtra margin introduced timing analysis to
into
consider the impacts seen in later stages
• Clock Uncertainty at block level
components
• Clock source (PLL) Glitter
• Clock tree introduced Applied all through
Glitter
• Sign-off timing the flow and for
margins signoff
• IR drop impact on timing
2
S
Clock Uncertainty
Stage wise timing margins to account for uncertainties
• Synthesis stage: Net delays + skew + cross talk + top
level impacts on blocks.
Applied
• At placement stage: skew + cross talk + top level impacts based on
on stages of the
HOW
blocks (due to crosstalk, clock divergence
• CTS etc)
stage: cross talk + top level impacts on
blocks
• Routing stage : top level impacts on blocks
Setup Slack(reg2reg) with Uncertainty
T setup
Tcoinb
T total
UFF0 1. 6ns UFF1
CLK CLK
T„ = T = 0.2
0. 1 ns ns
T„„ p = 0.2
CLK=500MHz ns 0. 1 ns
T '
told
CLK
0.8 ns
0. 5
ns
Hold Slack(reg2reg) with Uncertainty
T settip
Tcoinb
0. 2 ns
T told ' UFF0 UFF1
CLK CLK
T T =
0.2 ns
0. 2 ns
Tsetti '
CLK=500 MHz 0. 1 ns
T told '
CLK
0.3 0.8 ns
T insert.ainiU’=0. 3 ns
ns
CTS & Opt Quality Ohecks
• Setup & hold timing
• DRV (Clock and Data nets)
• Congestion
• Clock tree leading to congestion
• Setup/hold optimization leading to
congestion
• Utilization
• Utilization increase after CTS
• Utilization increase after setup/hold
optimization
36
• Number of hold buffers added
CTS & Opt Care about
• CTS buffer clustering
• CTS buffers leading to power density/dynamic IR issues
Decaps
• Clock duty cycle issues
• Clock tree induced jitter
• Cross-talk on Clock trees
CTS Distribution Methodologies — Cluster
Based
• Balanced clock tree - Most commonly used approach
• Based on location of clock sinks, group them into
clusters
• Build Tree for all individual clusters
• Balance clusters by adding buffers at the root of the
cluster
3S
CTS Distribution Methodologies — H-
tree
• Also Called Binary tree
• Each driver has 2
symmetric sinks
• Load/Routing all aspects should
be matched at every level.
• Can achieve very low skew
with reasonablebuffer/inv count
• May not be when
suitable related logic clock
on
domain sameto be scattered
have
CTS Distribution Methodologies — Clock
Mesh
• Generally used on high-
very speed design (like
Microprocessors) CLK
• Clock gating cells are spread
uniformly in design area
irrespective of clock sinks. CLK
• Based on placement, clock sinks cLOCK
are connected to clock
gating CLK
cells.
• Require advanced SPICE analysis
to find actual insertion delay and
skew 41
What Did We Learn?
• Impact of Clock tree delays on timing
• Understanding Clock distribution -
CTS
• CTS in ASIC Flow - Stages
• CTS Spec
• CTS QOR
• CTS care—abouts
• Clock distribution methodologies
