L4:Active series compensators:

Dynamic Voltage Restorers

Prof. Bhim Singh

Electrical Engineering Department
IIT Delhi, New Delhi
 OUTLINE
 Introduction
 Classification of DVR

 Principle of operation of DVR

 Control of DVR

 Analysis and Design of DVR

 Performance and simulation of DVR

 INTRODUCTION
Voltage quality problems
 sag
is vaf
 Swell iL
Critical Load
 voltage spikes, AC Mains
 surges,
 flickers,
 notches, DVR
 fluctuations,
vd
 waveform distortion,
 voltage imbalance,
 Harmonics etc

Solution is the DVRs (Dynamic Voltage Restorers)

They are extensive used for mitigating voltage based power quality
problems.
Now matured technology for providing compensation for the voltage
based power quality problems in ac distribution systems.

These compensating devices are also used

to regulate terminal voltage,
 to suppress voltage flicker and
to improve voltage balance in three-phase systems.

Development
varying configurations,
control strategies and
 solid-state devices.
Dynamic Voltage Restorers
PureWave: Dynamic Voltage Restorers
Dynamic Voltage Restorers
Dynamic Voltage Restorers
CLASSIFICATION OF ACTIVE SERIES COMPENSATORS
converter type
current source converter bridge structure
voltage source converter bridge structure.

The topology
shunt,
Series,
Hybrid

the number of phases

two wire (single-phase)
 three wire three-phase systems
 four wire three-phase systems.
Converter Based Classification
 is Tr iL

L Linear Load

AC Mains DVR

CSC Based Single-phase DVR

 is vaf iL
Critical Load

AC Mains

DVR

vd

It is lighter, cheaper and expandable to

VSC Based Single-phase DVR multilevel and multistep versions, to
enhance the performance with lower
switching frequencies
Popular in UPS based applications
Topology Based Classification
 Tr
is Zs
DVR

T1
AC Cd/2 Linear
Vs Loads
Mains
Lr T2
Cd/2

Half bridge topologies of VSI based Single-Phase Series DVR Filter

 Tr
is Zs
DVR

T1 T3
AC Linear
Vs Loads
Mains Cd
Lr T2 T4

Full bridge topologies of VSI based Single-Phase Series DVR

Filter
 vsa Tr
isa Zsa
Three-Phase
Tr Three-Wire
n Linear
vsb Loads
isb Zsb
Tr

vsc isc Zsc Cr Cr Cr

Lr Lr Lr
Cd

Three-Phase Three-Wire Active-Series DVR Filter

Supply System Based Classification
 Two Wire DVRs

Tr
is Zs
DVR

T1
AC Cd/2 Linear
Vs Loads
Mains
Lr T2
Cd/2

Half bridge topologies of VSI based

Single-Phase Series DVR Filter
 Tr
is Zs
DVR

T1 T3
AC Linear
Vs Loads
Mains Cd
Lr T2 T4

Full bridge topologies of VSI based

Single-Phase Series DVR Filter
 Three Wire DVRs

3-Phase 3-Wire DVRs

Rectifier Supported Battery Supported Capacitor supported

Left Shunt Right Shunt 3 single-phase VSC 3 single-phase VSC

3 single-phase VSC 3-leg VSC 3-leg VSC

3 single-phase VSC
3-leg VSC 2-leg VSC
2-leg VSC
3-leg VSC
2-leg VSC
2-leg VSC

Classification of configurations of DVR for three-phase three-wire

connected system
 vMa
ZSa vSa vCa vLa
iSa
vMb Tr vCb Three
ZSb vSb vLb
Phase
iSb Critical
vMc vLc Load
ZSc vSc vCc
iSc

AC/DC
VSI
converter

(a)

Schematic diagram of the left shunt rectifier supported DVR

connected system (a) 3-leg VSC based DVR
 vMa vLa
ZSa vSa vCa
iSa
vMb Tr Three
ZSb vSb vCb vLb
Phase
iSb Critical
vMc Load
ZSc vSc vCc vLc
iSc

AC/DC
VSI
converter

(b)
Schematic diagram of the left shunt rectifier supported DVR
connected system (b) 2-leg VSC based DVR
 vMa
ZSa vSa vCa vLa
iSa
vMb
ZSb vSb
Tr
vCb vLb Three
Phase
iSb Critical
vMc Load
ZSc vSc vCc vLc
iSc

AC/DC
VSI
converter

(c)
Schematic diagram of the left shunt rectifier supported DVR
connected system (c) 3 single phase VSC based DVR.
 vMa
ZSa vSa vCa vLa
iSa
vMb
ZSb vSb Tr
vCb vLb Three
Phase
iSb Critical
vMc Load
ZSc vSc vCc vLc
iSc

AC/DC
VSI
converter

(a)

Schematic diagram of the right shunt rectifier supported DVR connected system
(a) 3-leg VSC based DVR
 vMa vLa
ZSa vSa vCa
iSa
vMb Tr Three
ZSb vSb vCb vLb Phase
iSb Critical
vMc Load
ZSc vSc vCc vLc
iSc

AC/DC
VSI
converter

(b)

Schematic diagram of the right shunt rectifier supported DVR connected system
(a) 3-leg VSC based DVR (b) 2-leg VSC based DVR
 vMa
ZSa vSa vCa vLa
iSa
vMb Tr vLb Three
ZSb vSb vCb
Phase
iSb Critical
vMc Load
ZSc vSc vCc vLc
iSc

AC/DC
converter

(c)
Schematic diagram of the right shunt rectifier supported DVR connected system
(c) 3 single phase VSC based DVR
 vMa vLa
ZSa vSa vCa
iSa
vMb Tr Three
ZSb vSb vCb vLb
Phase
iSb Critical
vMc vLc Load
ZSc vSc vCc
iSc

Battery DC/DC

+
-

(a)

Schematic diagram of the BESS supported DVR connected system (a) 3-leg VSC
based DVR
 vMa vLa
ZSavSa vCa
iSa
vMb Tr Three
ZSb vSb vCb vLb
Phase
iSb Critical
vMc Load
ZSc vSc vCc vLc
iSc

Battery
DC/DC

+
-

(b)

Schematic diagram of the BESS supported DVR connected system (b) 2-leg VSC
based DVR
 vMa
ZSa vSa vCa vLa
iSa
vMb vLb Three
ZSb vSb
Tr
vCb
Phase
iSb Critical
vMc Load
ZSc vSc vCc vLc
iSc

Battery
DC/DC

+
-

(c)

Schematic diagram of the BESS supported DVR connected system (c) 3 single phas
VSC based DVR.
 vMa
ZSa vSa vCa vLa
iSa
vMb Three
ZSb vSb
Tr
vCb vLb
Phase
iSb Critical
vMc Load
ZSc vSc vCc vLc
iSc

(a)

Schematic diagram of the capacitor supported DVR connected system (a) 3-

leg VSC based DVR
 vMa
ZSa vSa vCa vLa
iSa
vMb Three
ZSb vSb
Tr vLb
vCb
Phase
iSb Critical
vMc Load
ZScvSc vC vLc
iSc

(b)

Schematic diagram of the capacitor supported DVR connected system (b) 2-

leg VSC based DVR
 vMa vLa
ZSa vSa vCa
iSa
vMb Tr Three
ZSb vSb vCb vLb
Phase
iSb Critical
vMc Load
ZSc vSc vCc vLc
iSc

(c)

Schematic diagram of the capacitor supported DVR connected system (c) 3

single phase VSC based DVR.
 ZSa vSa vLa
vCa
iSa
vMa Three
vSb Tr
ZSb vCb vLb Phase
Critical
iSb
vMb Loads
Tr
ZSc vSc vCc vLc

iSc
vMc Tr

Cr Rr Cr Rr Cr Rr
Lr Lr Lr
BESS

VSC

Fig. Schematic diagram of the BESS supported

DVR connected system.
 vSa vLa
ZSa vCa
iSa
vMa Three
vSb Tr
ZSb vCb vLb Phase
Critical
iSb
vMb Loads
Tr
ZSc vSc vCc vLc

iSc
vMc Tr

Cr Rr Cr Rr Cr Rr
Lr Lr Lr

vdc
Cdc
VSC

Fig. Schematic diagram of capacitor supported DVR connected

system
Phasor diagram for capacitor supported DVR under (a) voltage
sag, (b) swell, (c) unbalanced sag
Principle of Operation of Active
Series Compensators
 Principle of Operation of Active Series
Compensators
The series active compensators are based on the principle of injecting a
voltage in series with the supply and this is implemented in two ways.

This compensator is to insert a voltage of required waveform so that it can

protect sensitive consumer loads from supply disturbances such as sag,
swell, unbalance harmonics etc in supply voltage and are known as
dynamic voltage restorers (DVRs).

A voltage (Vinj) is inserted such that the load voltage (VL) is constant in
magnitude and undistorted, though the supply voltage (VS) is not constant in
magnitude or distorted.

The VL(pre-sag) is the voltage across the critical load prior to voltage sag
condition.
 VM
ZS VS VL
Vinj
Critical
Load
IL
Source

Voltage
DVR Source BESS
Converter

(a)

Vload4
Vload3
VL(pre-sag)
Vinj4 Vinj3
Vload2
 Vinj2
Vload1
Vs Vinj1
IL

(b)

Fig. (a) Single line diagram of DVR (b) Phasor diagram of the DVR voltage
injection schemes.
During the sag, the voltage is reduced to VS with a phase lag angle of θ.
Now the DVR injects a voltage so that the load voltage magnitude is
maintained at the pre-sag condition.
 According to the phase angle of the load voltage, the injection of voltages
can be realized in four ways .

Vinj1 represents the voltage-injected in-phase with the supply voltage.

With the injection of Vinj2, the load voltage magnitude remains same but it
leads VS by a small angle.

In Vinj3, the load voltage retains the same phase as that of the pre-sag
condition, which may be an optimum angle considering the energy source.

Vinj4 is the condition where the injected voltage is in quadrature with the
current and this case is suitable for a capacitor supported DVR as this
injection involves no active power.
However, the minimum possible rating of the converter is achieved by the
Vinj1.
The DVR is operated in this scheme with a battery energy storage system
(BESS).
Control of Active Series Compensators
 Control of DSTATCOM
The performance of the DVR depends on the control algorithm.

Some of the time domain control algorithms.

 Synchronous Reference Frame (SRF) Theory or also known as d-q Theory
 Unit Template Technique or PI (Proportional-Integral) Controller Based Theory
 Instantaneous Reactive Power Theory (IRPT) or PQ Theory or α-β Theory
 Instantaneous Symmetrical Component (ISC) Theory
 Neural Network Theory (Widrow Derived LMS based Adaline Algorithm)
 Singe-Phase PQ Theory
 Singe-Phase DQ Theory
 Enhanced Phase Locked Loop (EPLL) based Control Algorithm
 Adaptive Detecting Algorithm also known as Adaptive Interference Cancelling
Theory
And many more
 Frequency domain control algorithms
•Fourier Series Theory
•Discrete Fourier Transform Theory
•Fast Fourier Transform Theory
•Recursive Discrete Fourier Transform Theory
•Kalman Filter based Control Algorithm
•Wavelet Transformation Theory
•Stock-well Transformation (S-Transform) Theory
•Empirical Decomposition (EMD) Transformation Theory
•Hilbert Huang Transformation Theory
•And many more
Synchronous Reference Frame Theory (SRFT) Based Control of DVR
vSa vSd vCd
+
abc - PI

+
-
controller abc

+
vSb +

vSc d-q-0 vSq + vCq - d-q-0

- + PI

+
controller

+
vCa* vCb* vCc*
2
Three
phase PLL 2
vCa
Voltage
(cos θ,sin θ ) * vCb controlled
vCd
PWM
vLd Controller
vLa abc - vCc
+
vLb
vLc d-q-0 vLq
+-
vCq*
Gate Pulses for
vL * the VSC of DVR

abc vLd*
Reference
Load voltage
Generation d-q-0
vLq*

Fig. Synchronous reference frame theory (SRFT) based method of

control for BESS supported DVR
 V *
dc + PI
- controller
v LPF
dc v
loss
v *
v v v v * La
sa abc Sd ddc - d
LPF + abc
v
sb v *
v d-q-0 Lb
v d-q-0 Sq LPF
sc +
v + v *
qdc v* Lc
q

i v 2
La 2 qr
Three
i
Lb phase PLL
i (cos θ,sin θ ) v Voltage
Lc La controlled
v v PWM
L Lb
v Controller
La v
v Lc
Lb Amplitude - PI
+ controller
v
Lc Gate Pulses for the VSC of
DVR
v *
L

Synchronous reference frame theory (SRFT) based control for capacitor supported
DVR.
 Vdc* PI
+- controller
Vdc
iLd iddc +
iLa LPF +
abc dq0
iLb dq iLq iqdc abc
iLc LPF +
+
vLa sin cos sin cos
vLb 3- Phase
vLc PLL
iSa*
VL PI PWM
Amplitude -
calculation + controller Gate Gate pulse
Pulses generator iSb*
VL *
iSc*

iSc iSb iSc

Fig. Current mode control scheme of the DVR.

ANALYSIS AND DESIGN OF ACTIVE SERIES COMPENSATORS

The design of DVR includes

the voltage rating of VSC of DVR,

the current rating of VSC of DVR,
 the kVA rating of VSC of DVR,
 injection transformer rating,
dc bus voltage,
dc bus capacitance,
ac interfacing inductance and
 the ripple filter.
Design of Voltage Rating of VSC of DVR

Considering a voltage fluctuation between +20% and –30% and 6%

voltage unbalance in the terminal voltage and for a three-phase 415 V, 20
kVA, 50 Hz critical load, the voltage rating of VSC of DVR depends on the
maximum voltage to be injected in this condition of critical load.

Therefore, the voltage injection per phase is 30 % of the phase voltage

and hence the VSC voltage rating is calculated for this requirement of the
load. The maximum sag in the source terminal voltage is obtained as
239.6 *0.7= 167.72 V.

Therefore, the injected voltage (VC) is as,

VC = (VS2-VL2) = (239.62-167.722) = 171.1 V.

Design of Current Rating of VSC of DVR

The current rating of DVR depends on the load connected to the downstream of
DVR. For a 20 kVA load, the current is calculated as,
3 Vs IS = 20000

where, IS is the current and VS is the line voltage.

Therefore, the current rating of DVR is as,
Current rating, IS = 27.82 A.

kVA Rating of VSC of DVR

The kVA rating of VSC of DVR is calculated as,

kVA= 3 VC IS/1000 = 14.28 kVA .
Rating of an Injection Transformer of DVR

The injection transformer is designed considering the optimum

voltage level of the VSC.

For a step-down in the converter voltage, the transformer is

selected such that the primary winding is 171.10 V and the
secondary is to be of 50 V so that the VSC is connected on the 50 V
side.

The kVA rating of the injection transformer is same as that of VSC

rating and is calculated as,
kVA= 3VC IS/1000 = 14.28 kVA

Hence the rating of the injection transformer is 14.27 kVA, 171

V/50 V.
DC Capacitor Voltage of VSC of DVR

The dc capacitor voltage is selected based on the following

relation,
Vdc > 22 VC (s),

where, the converter voltage (VC (s)) is 50 V. The value of Vdc is

obtained as 141.4 V and a Vdc of 150V is selected for the DVR.
 DC Capacitance of VSC of DVR

The dc bus capacitance is selected based on the transient energy

required during change in load. Considering the energy stored in the
capacitor is for meeting the energy demand of the load for a fraction of
power cycle, the relation can be expressed as,
(1/2)Cdc (Vdc2- Vdc12) = 3VphIph t

where, Vdc is the rated voltage and Vdc1 is the drop in dc bus voltage
allowed during transients and t is the time for which support is required.
Considering t = 200µsec, Vdc= 150 V, Vdc1= 150- 5% of 150 = 142.5 V
and Cdc is the dc bus capacitance.
1/2 * Cdc(1502-142.52) = 3*239.6*27.82*0.20 ms

Cdc = 3.64 mF
Hence, a dc bus capacitor of 3700 µF, 160 V is selected for the DVR.
 Interfacing Inductor for VSC of DVR

The interfacing inductance (Lr) is selected based on the current ripple in

the current of the DVR and by considering ripple current in the inductor is
5%, the inductor is calculated as,
Lr = 0.866mVdc/(6afsI)

Lr = 0.866*1*150/{6*1.2*10k*(0.05*95.1)} = 0.379 mH

Hence, an interfacing inductor (Lr) of 1.0 mH and 100A current carrying capacity
is selected for the DVR.
Ripple Filter
The ripple filter is designed based on the switching frequency. It is
designed that the capacitor offers a low impedance path for the switching
ripple and the series inductor should provide high impedance for the
switching ripple.

The reactance given by the capacitor and inductor at half of the switching
frequency (fs = 10 kHz), i.e, fr = fs/2 is calculated as,

XCr=1/(2*π* fr *Cr)=1/(2*3.14*5000*Cr)

XLr=2*π* fr *Lr=2*3.14*5000*Lr

Considering, XCr = 3 Ω, Cr = 10.61 μF

XLr = 100 Ω, Lr = 3.18 mH
These values of ripple filter elements are initially used for simulation and
by iteration it is found that, Lr= 3.5 mH, Cr = 10 μF is suitable for minimum
ripples at the output voltage of DVR.
MODELING, SIMULATION AND PERFORMANCE OF ACTIVE SERIES
COMPENSATORS
Performance of Synchronous Reference Frame Theory based BESS
Supported DVR

The PCC voltages (vS), load voltages (vL), DVR voltages (vC), amplitude
of load voltage (VL) and PCC voltage (VS), source currents (iS), reference
load voltages (vL*) and dc bus voltage (vdc) are also depicted in Fig.
Dynamic performance of DVR with in-phase injection during
voltage sag and swell applied to critical load.
Voltages at PCC and Load terminal.
Dynamic performance of DVR during harmonics in supply
voltage applied to critical load.
 (b)
(a)
 (c)

Fig. THD and harmonic spectra of PCC (a) PCC voltage, (b) source
current and (c) Load voltage.
 Table
Comparison of DVR Rating for Sag Mitigation

Scheme1 Scheme 2 Scheme3 Scheme4

Phase Voltage(V)
90 100 121 135

PhaseCurrent (A)
13 13 13 13

VA perphase
1170 1300 1573 1755

KVA (% of Load)
37.5% 41.67% 50.42% 56.25%
Performance of SRF Controlled Capacitor Supported DVR
Fig. Compensation of supply voltage sag using SRF controlled
capacitor supported DVR.
Fig. Compensation of supply voltage swell using SRF controlled
capacitor supported DVR
Fig. Compensation of supply voltage unbalance using SRF controlled
capacitor supported DVR
Fig. Compensation of supply voltage harmonics using SRF controlled
capacitor supported DVR
 (b)

(a)

Fig. THD and harmonic spectra of (a)

PCC voltage, (b) source current and
(c) Load voltage.

(c)
Performance of Current Mode Controlled DVR
Fig. Dynamic behavior of Adaline based NN controlled DVR for
voltage sag compensation
Fig. Dynamic behavior of DVR for voltage swell
compensation.
 (b)

(a)

Fig.THD and harmonic spectra of (a)

Load voltage, (b PCC) voltage and (c)
source current

(c)
NUMERICAL EXAMPLES
Q.1 A single-phase AC supply has ac mains has a voltage of 230 V at 50Hz and
feeder (source) impedance of 0.5 ohms resistance and 2.5 ohms inductive
reactance. It feeds a single-phase load of a Zl= (24+ j18) ohms. Calculate (a) the
voltage drop across the source impedance, (b) the voltage across the load. If a
PWM synchronous static series compensator (SSSC) is used to raise the voltage to
same as the input voltage (230 V) with minimum rating, calculate (c) the voltage
rating of the compensator, (d) the current rating of the compensator, and (e) the VA
rating of the compensator.

ZS=5-j2.0 pu

Tr
is Zl=24+j18 Ω
DVR
T1 T3

vs AC
Mains
Cd
Lr T2 T4
Linear
Loads
Solution: Given that, VS = 230 V rms, f=50 Hz, a single-phase load
(ZL=24+j18) ohms has an input ac voltage of 230 V, 50Hz, AC supply
and source impedance of ZS=(0.5+j2.5) ohms.
The total impedance, ZS+ZL=24+j18+0.5+j2.5=24.5+j20.5=31.945Ω
The load current before compensation is as.
IS=VS/(ZS+ZL)=230/31.945=7.19 A.
1) The voltage drop across the source impedance, VZS=ZS*IS=18.33 V.
2) The voltage across the load, VZL=ZL*IS=215.70V.
ZS=2.5495 , ZL=30
The series connected PWM synchronous static series compensator
(SSSC) is used to raise the load terminal voltage to same value as input
voltage (230 V). The SSSC must compensate the voltage drop across
the source impedance.
Since the voltage across the load is as source voltage, VL=VS=230V, the
load current, I'L=VS/ZL=230/30=7.67 A.
Therefore, the supply current is as. I = I'L=VS/ZL=230/30=7.67A.
V'ZL=230 , V'ZS=I'LZS=7.67 2.5495 =19.55 V
3. The voltage rating of the compensator, Vsssc=VS- V'ZS –V'ZL =19.54 V.
4. The current rating of the compensator, Isssc=I=7.67A.
5. The VA rating of the compensator is as, S=VssscIsssc=140.72VA.
Q.2 A three-phase, three-wire AC supply has ac mains voltage of 440
V at 50Hz and feeder (source) impedance of 0.25 ohms /phase
resistance and 2.5 ohms/phase inductive reactance. It feeds a three-
phase star connected load Z= (24+j18) ohms/phase. Calculate (a) the
voltage drop across the source impedance, (b) the voltage across the
load. If a PWM synchronous static series compensator (SSSC) is
used to raise the voltage to same as the input voltage (440V) with
minimum rating, calculate (c) the voltage rating of the compensator,
(d) the current rating of the compensator, and (e) the VA rating of the
compensator. Z=24+j18 Ω/phase
Tr a
vsa isa Zsa
Tr

vsb Zsb
isb
Tr c b

vsc isc Zsc Cr Cr Cr Three- Phase

Three-Wire
Linear Load

Lr Lr Lr
Cd
Solution: Given that,, VS = 440/√3=254V, f=50 Hz, a three-phase load
(ZL=24+j18) ohms has an input per phase ac voltage of 254 V, 50Hz, AC
supply and source impedance of ZS=(0.25+j2.5) ohms.
The total impedance, ZS+ZL=0.25+j2.5+24+j18=24.25+j20.5=31.754 Ω
The load current before compensation is as. IS=VS/(ZS+ZL)=254/31.754=7.999
A.
1. The voltage drop across the source impedance, VZS=ZS*IS=20.09 V.
2. The voltage across the load, VZL=ZL*IS=239.97 V.
ZS=2.5124 , ZL=30
The series connected PWM synchronous static series compensator (SSSC) is
used to raise the load terminal voltage to same value as input voltage (254 V).
The SSSC must compensate the voltage drop across the source impedance.
Since the voltage across the load is as source voltage, VL=VS=254V, The load
current, IL=VS/ZL=254/30=8.4667 A.
Therefore, the supply current is as. I= IL=VS/ZL=254/30=8.4667A. (Since the
all circuit elements are connected in series.)
VZL=254 ,VZS=ILZS=8.4667 2.5124 =20.2716 V
3. The voltage rating of the compensator, Vsssc= + VZS +VZL -VS = 2.27 V.
4. The current rating of the compensator, Isssc=I=8.4667A
5. The VA rating of the compensator, S=3VssscIsssc=510.6VA.
.
Thank You