📌 SPI Core/Controller Verification Course Plan (Industry-Standard
Steps)
Duration: 4-5 Weeks (Daily 2 Hours)
Focus: Verifying an Existing SPI Core using UVM, RAL, Virtual Sequences, Regression
Automation
Final Outcome: Students will verify a pre-existing SPI Core design using an industry-
standard UVM testbench
Includes: Hands-on Tasks & Project Deliverables for each stage
Follows Industry Steps: Requirement Analysis → Test Plan → Testbench
Implementation → Coverage & Regression
Prerequisites
Students should have:
Basic Verilog/SystemVerilog (Testbench structures, procedural blocks)
Basic UVM Concepts (Driver, Monitor, Sequencer, Agent, Environment)
APB Protocol Basics (Read/Write Transactions)
Understanding of Makefile & TCL for simulation automation
Industry Standard Verification Flow
1. Specification Understanding & Test Plan Creation
Day 1: Understanding SPI Protocol & Functional Requirements
Task: Read & analyze SPI Core specifications, prepare functional block diagram
Day 2: Understanding APB Interface & System-Level Design
Task: Study APB protocol, analyze integration with SPI
Day 3: Test Plan Development (Features, Functional Coverage, Assertions)
Task: Define verification goals, list test scenarios, create coverage plan
Day 4: Testbench Architecture (UVM Components & Hierarchy Planning)
Task: Define testbench structure, create block diagram for UVM components
2. UVM Testbench Development
Day 5: Setting Up UVM Testbench Framework (Folder Structure, File Hierarchy)
Task: Create directory structure, add UVM base files
Day 6: Writing SPI & APB Interfaces in UVM
Task: Implement and test a UVM interface for SPI & APB
Day 7: Implementing UVM Agent (Driver, Monitor, Sequencer)
Task: Develop SPI driver & monitor with transaction class
Day 8: Implementing APB Agent & Integrating with SPI Agent
Task: Write an APB agent and test simple read/write transactions
Day 9: Building UVM Environment (Connecting Agents & Scoreboard)
Task: Implement an environment class that connects APB & SPI agents
Day 10: Writing Base Test & Connecting to DUT
Task: Create a base test that initializes the UVM testbench
3. Stimulus Development & RAL Model
Day 11: Implementing SPI & APB Transactions
Task: Write APB-to-SPI transactions to drive stimulus
Day 12: Understanding Virtual Sequences & Virtual Sequencer
Task: Implement a Virtual Sequencer to connect APB & SPI sequences
Day 13: Writing Virtual Sequence for SPI & APB Interaction
Task: Develop a virtual sequence that drives APB & SPI together
Day 14: Introduction to RAL (Register Abstraction Layer)
Task: Generate a basic RAL model for SPI Core
Day 15: Generating RAL Model for SPI Registers
Task: Write a UVM sequence that accesses SPI registers using RAL
Day 16: Writing RAL-Based Sequences & Bus Sequences
Task: Develop bus sequences and compare them with RAL sequences
4. Functional Coverage, Assertions & Regression
Day 17: Implementing Functional Coverage for SPI Transactions
Task: Define coverage points for SPI transactions
Day 18: Writing Protocol Assertions for SPI Signals
Task: Implement UVM assertions to check SPI protocol compliance
Day 19: Automating Simulation with Makefile & TCL Scripts
Task: Write a Makefile & TCL script to run regressions
Day 20: Running Regression & Debugging Failures
Task: Execute regression and analyze failures using logs & waveforms
Day 21: Optimizing UVM Testbench for Coverage & Performance
Task: Improve test coverage and optimize test execution time
5. Final Verification & Project Submission
Day 22: Running Full Regression on SPI Core
Task: Execute a complete regression suite with all testcases
Day 23: Debugging Issues Using Logs & Waveforms
Task: Identify and fix testbench issues using logs & waveforms
Day 24: Final Project Report & Completion
Task: Prepare a verification report summarizing findings and improvements
Final Project
Students will verify a pre-existing SPI Core design using UVM, RAL, Virtual Sequences,
and Regression Automation.
They will generate coverage reports, analyze failures, and debug issues using industry-
standard tools.
Final Deliverables:
• Complete UVM Testbench
• Verification Plan & Test Plan
• Functional Coverage Report
• Regression Results & Debugging Report
Adjustments Based on Your Requirements
No RTL Design Teaching – Focus only on testbench & verification
Use Pre-Built SPI Core – No need to design from scratch
Real-World Verification Tasks – Hands-on assignments & debugging tasks
Industry-Standard Verification Flow – Specification → Test Plan → TB Architecture →
Coverage → Regression
Note: The sequence and content of classes may be modified to accommodate the learning
pace and specific needs of students.
TB Architecture: For SPI core verification [not QSPI]
