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Design Rules: Jan M. Rabaey

The document discusses design rules for integrated circuits. It provides guidelines for constructing process masks and minimum feature sizes. It also details the different layers involved in CMOS technology like wells, polysilicon, and metals and shows examples of design rules for spacing within and between layers like transistors, contacts, and vias.

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prakashrout
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60 views9 pages

Design Rules: Jan M. Rabaey

The document discusses design rules for integrated circuits. It provides guidelines for constructing process masks and minimum feature sizes. It also details the different layers involved in CMOS technology like wells, polysilicon, and metals and shows examples of design rules for spacing within and between layers like transistors, contacts, and vias.

Uploaded by

prakashrout
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Design Rules

Jan M. Rabaey

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Cross-Section of CMOS Technology

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Design Rules

Interface between designer and process


engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

CMOS Process Layers


Layer

Color

Well (p,n)

Yellow

Active Area (n+,p+)

Green

Select (p+,n+)

Green

Polysilicon

Red

Metal1

Blue

Metal2

Magenta

Contact To Poly

Black

Contact To Diffusion

Black

Via

Black

Digital Integrated Circuits

Design Rules

Representation

Prentice Hall 1995

Intra-Layer Design Rules


SamePotential
Well
10

0
or
6

DifferentPotential
2

9
Polysilicon
2

Active
3

Metal1
Contact
orVia
Hole

2
2

Select

3
4

Metal2
3

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Transistor

Transistor Layout

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Vias and Contacts


2
4

Via
1

Metalto
1
ActiveContact

1
Metalto
PolyContact
3

Digital Integrated Circuits

Design Rules

Prentice Hall 1995

Select Layer
2
3

Select
2

1
3

Well

Substrate
Digital Integrated Circuits

Design Rules

Prentice Hall 1995

CMOS Inverter Layout


In

GND

VD D

Out
(a)Layout

A
n

psubstrate
n

Field
Oxide

(b)CrossSectionalongAA
Digital Integrated Circuits

Design Rules

Prentice Hall 1995

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