Encoder and Decoder
4:2 ENCODER
• An encoder is a digital circuit
that converts a set of binary
inputs into a unique binary
code.
• An encoder is a combinational
circuit that takes 2ⁿ input lines and
produces n output lines.
• 2ⁿ to n Encoder
2
Structural Modeling
module encoder4to2(
input D0, D1, D2, D3,
output Y1, Y0
);
or or1(Y0, D1, D3); // Y0 = D1 + D3
or or2(Y1, D2, D3); // Y1 = D2 + D3
3
endmodule
module tb_encoder4to2;
reg D0, D1, D2, D3;
wire Y1, Y0;
encoder4to2 uut (.D0(D0),.D1(D1),.D2(D2),.D3(D3), .Y1(Y1),.Y0(Y0));
initial begin
$display("Time | D3 D2 D1 D0 | Y1 Y0");
$monitor("%4dns | %b %b %b %b | %b %b", $time, D3, D2, D1, D0, Y1, Y0);
D3 = 0; D2 = 0; D1 = 0; D0 = 1; #10; // Expect Y1Y0 = 00
D3 = 0; D2 = 0; D1 = 1; D0 = 0; #10; // Expect Y1Y0 = 01
D3 = 0; D2 = 1; D1 = 0; D0 = 0; #10; // Expect Y1Y0 = 10
D3 = 1; D2 = 0; D1 = 0; D0 = 0; #10; // Expect Y1Y0 = 11
D3 = 1; D2 = 1; D1 = 0; D0 = 0; #10; // May still produce Y1Y0 = 11
$finish;
end
endmodule
Simulation
Dataflow Modeling
module encoder4to2 (
input [3:0] D,
output wire [1:0] Y
);
assign Y[0] = D[1] | D[3]; // Y0 = D1 + D3
assign Y[1] = D[2] | D[3]; // Y1 = D2 + D3
6
endmodule
IF STATEMENT :
Cascaded if else if else if else statements are also possible
module encoder4to2(
input D0, D1, D2, D3,
output reg Y1, Y0
);
always @(*) begin
if (D3) begin
Y1 = 1;
Y0 = 1;
end else if (D2) begin
Y1 = 1;
Y0 = 0;
end else if (D1) begin
Y1 = 0;
Y0 = 1;
end else if (D0) begin
Y1 = 0;
Y0 = 0;
end else begin
Y1 = 0;
Y0 = 0; // default if none is active
end
end
endmodule
case statements
The case statement has a total of three variations: case, casex and casez. .
The case statement matches the value exactly against each case label.
If an exact match is not found, the default statement will be executed.
case (expression)
value1: statement1;
value2: statement2;
default: statement_default;
endcase
casex,casez: considers all x and z values as don’t care.
always @(*) begin
casex (opcode)
4'b1xx0: action = 1; // matches any input with MSB=1 and LSB=0
4'b01x1: action = 2;
default: action = 0;
endcase
end
Behavioral Modeling
module encoder4to2 (
input [3:0] D,
output reg [1:0] Y
);
always @(*) begin
case (D)
4'b0001: Y = 2'b00;
4'b0010: Y = 2'b01;
4'b0100: Y = 2'b10; 11
4'b1000: Y = 2'b11;
default: Y = 2'b00;
endcase
endmodule
Priority Encoder
● The priority encoder is a combinational logic circuit that contains 2^n
input lines and n output lines and represents the highest priority input
among all the input lines.
● When multiple input lines are active high at the same time, then the
input that has the highest priority is considered first to generate the
output.
4:2 Priority Encoder
module priority_encoder_4to2 (
input D3, D2, D1, D0,
output reg Y1, Y0
);
always @(*) begin
// Priority: D3 > D2 > D1 > D0
casex ({D3, D2, D1, D0})
4'b1xxx: {Y1, Y0} = 2'b11; // D3
4'b01xx: {Y1, Y0} = 2'b10; // D2
4'b001x: {Y1, Y0} = 2'b01; // D1
4'b0001: {Y1, Y0} = 2'b00; // D0
default: {Y1, Y0} = 2'b00; // No input is high
endcase
end
endmodule
module tb_priority_encoder_4to2;
reg D3, D2, D1, D0;
wire Y1, Y0;
priority_encoder_4to2 uut (
.D3(D3), .D2(D2), .D1(D1), .D0(D0),
.Y1(Y1), .Y0(Y0)
);
initial begin
$display("Time | D3 D2 D1 D0 | Y1 Y0");
$monitor("%4dns | %b %b %b %b | %b %b", $time, D3, D2, D1, D0, Y1, Y0);
{D3, D2, D1, D0} = 4'b0001; #10; // D0 -> 00
{D3, D2, D1, D0} = 4'b0010; #10; // D1 -> 01
{D3, D2, D1, D0} = 4'b0100; #10; // D2 -> 10
{D3, D2, D1, D0} = 4'b1000; #10; // D3 -> 11
// Multiple inputs high - higher priority should be selected
{D3, D2, D1, D0} = 4'b1011; #10; // D3 > D2 > D1 > D0 -> 11
{D3, D2, D1, D0} = 4'b0011; #10; // D1 > D0 -> 01
{D3, D2, D1, D0} = 4'b0000; #10; // None high -> 00
$finish;
end
endmodule
8:3 Priority Encoder
module priority_encoder(
input [7:0] D, // Inputs D7 (MSB) to D0 (LSB)
output reg [2:0] Y // Outputs A (MSB), B, C (LSB)
);
always @(*) begin
casex (D)
8'b1xxxxxxx: Y = 3'b111; // D7 is highest priority
8'b01xxxxxx: Y = 3'b110; // D6
8'b001xxxxx: Y = 3'b101; // D5
8'b0001xxxx: Y = 3'b100; // D4
8'b00001xxx: Y = 3'b011; // D3
8'b000001xx: Y = 3'b010; // D2
8'b0000001x: Y = 3'b001; // D1
8'b00000001: Y = 3'b000; // D0
default: Y = 3'b000; // No input is high - default output
endcase
end
endmodule
module priority_encoder_tb();
reg [7:0] D;
wire [2:0] Y;
priority_encoder uut ( .D(D),.Y(Y));
initial begin
$display("Time\t D\t\tY");
$monitor("%0dns\t %b\t %b", $time, D, Y);
D = 8'b00000000; #10; // No input is high, expect Y = 000
D = 8'b00000001; #10; // D0 high => Y = 000
D = 8'b00000010; #10; // D1 high => Y = 001
D = 8'b00000100; #10; // D2 high => Y = 010
D = 8'b00001000; #10; // D3 high => Y = 011
D = 8'b00010000; #10; // D4 high => Y = 100
D = 8'b00100000; #10; // D5 high => Y = 101
D = 8'b01000000; #10; // D6 high => Y = 110
D = 8'b10000000; #10; // D7 high => Y = 111
D = 8'b11000001; #10; // D7 and D6 and D0 high => Y = 111
D = 8'b00111000; #10; // D5, D4, D3 high => Y = 101
D = 8'b00000011; #10; // D1 and D0 high => Y = 001
$finish;
end
endmodule
Simulation
2:4 DECODER
• A decoder is a combination logic
circuit that is capable of identifying
or detecting a particular code.
• A Decoder takes n input lines and
activates one of 2ⁿ output lines.
• n to 2ⁿ Decoder
20
Structural Modeling
module decoder2to4 (
input a, b, e,
output Y0, Y1, Y2, Y3
);
wire na, nb;
not not_a(na, a);
not not_b(nb, b);
and and0(Y0, na, nb, e); // 00 21
and and1(Y1, na, b, e); // 01
and and2(Y2, a, nb, e); // 10
and and3(Y3, a, b, e); // 11
endmodule
Dataflow Modeling
module decoder2to4 (
input a, b, e,
output wire Y0, Y1, Y2, Y3
);
assign Y0 = e & ~a & ~b;
assign Y1 = e & ~a & b;
assign Y2 = e & a & ~b; 22
assign Y3 = e & a & b;
endmodule
module tb_decoder2to4;
reg a, b, e;
wire Y0, Y1, Y2, Y3;
decoder2to4 uut (.a(a), .b(b), .e(e), .Y0(Y0), .Y1(Y1), .Y2(Y2), .Y3(Y3));
initial begin
$display("Time | e a b | Y0 Y1 Y2 Y3");
$monitor("%4dns | %b %b %b | %b %b %b %b", $time, e, a, b, Y0, Y1, Y2, Y3);
e = 1; a = 0; b = 0; #10; // Expect Y0 = 1
e = 1; a = 0; b = 1; #10; // Expect Y1 = 1
e = 1; a = 1; b = 0; #10; // Expect Y2 = 1
e = 1; a = 1; b = 1; #10; // Expect Y3 = 1
e = 0; a = 0; b = 0; #10;
e = 0; a = 0; b = 1; #10;
e = 0; a = 1; b = 0; #10;
e = 0; a = 1; b = 1; #10;
$finish;
end
endmodule
Simulation
Behavioral Modeling
module decoder2to4 (
input a, b, e,
output reg Y0, Y1, Y2, Y3
);
always @(*) begin
if (e) begin
case ({a, b})
2'b00: Y0 = 1;
2'b01: Y1 = 1;
2'b10: Y2 = 1; 25
2'b11: Y3 = 1;
endcase
end
end
endmodule
2 TO 4 DECODER
module decoder2_4(
input [1:0]in,
output [3:0]out
);
reg out;
always @ (*)
begin
case (in)
2'b00:out=4'b0001;
2'b01:out=4'b0010;
2'b10:out=4'b0100; 26
2'b11:out=4'b1000;
endcase
end
endmodule
2 TO 4 DECODER TEST BENCH
module decoder2_4_tb();
reg [1:0]in;
wire [3:0]out;
decoder2_4 dut(.in(in),.out(out));
initial
begin
in=2'b01;
#200;
in=2'b11; 27
#200
$stop;
end
endmodule
Full Adder using decoder
module full_adder_decoder (
input A, B, Cin,
output S, Cout
);
wire [7:0] m; // Decoder outputs m0 to m7
// 3-to-8 decoder logic
assign m[0] = ~A & ~B & ~Cin;
assign m[1] = ~A & ~B & Cin;
assign m[2] = ~A & B & ~Cin;
assign m[3] = ~A & B & Cin;
assign m[4] = A & ~B & ~Cin;
assign m[5] = A & ~B & Cin;
assign m[6] = A & B & ~Cin;
assign m[7] = A & B & Cin;
// Full Adder output logic using minterms
assign S = m[1] | m[2] | m[4] | m[7]; // Minterms with S = 1
assign Cout = m[3] | m[5] | m[6] | m[7]; // Minterms with Cout = 1
endmodule
module tb_full_adder_decoder;
reg A, B, Cin;
wire S, Cout;
full_adder_decoder uut (
.A(A), .B(B), .Cin(Cin),
.S(S), .Cout(Cout)
);
initial begin
$display("A B Cin | S Cout");
$monitor("%b %b %b | %b %b", A, B, Cin, S, Cout);
A = 0; B = 0; Cin = 0; #10;
A = 0; B = 0; Cin = 1; #10;
A = 0; B = 1; Cin = 0; #10;
A = 0; B = 1; Cin = 1; #10;
A = 1; B = 0; Cin = 0; #10;
A = 1; B = 0; Cin = 1; #10;
A = 1; B = 1; Cin = 0; #10;
A = 1; B = 1; Cin = 1; #10;
$finish;
end
endmodule
Simulation
