Dr. N. Karuppiah & Dr. S.
Ravivarman
requests. This also accepts interrupt acknowledge (INTA) signal from CPU that
causes the 8259A to release vector address on to the data bus.
Data Bus Buffer: This tristate bidirectional buffer interfaces internal
8259A bus to the microprocessor system data bus. Control words, status and
vector information pass through buffer during read or write operations.
Read write Control Logic: This circuit accepts and decodes commands
from the CPU. This also allows the status of the 8259A to be transferred on to
the data bus.
Cascade Buffer/Comparator: This block stores and compares the ID's of
all the 8259As used in the system. The three I/O pins CAS0-2 are outputs, when
the 8259A is used as a master. The same pins act as inputs when the 8259A is in
slave mode. The 8259A in master mode sends the ID of the interrupting slave
device on these lines. The slave thus selected, will send its pre-programmed
vector address on the data bus during the next INTA pulse.
Interrupt Sequence
The powerful features of the 8259A in a microcomputer system are its
programmability and the interrupt routine addressing capability. The latter
allows direct or indirect jumping to the specific interrupt routine requested
without any polling of the interrupting devices. The normal sequence of events
during an interrupt depends on the type of CPU being used. The events occur as
follows in an 8085 system:
1. One or more of the INTERRUPT REQUEST lines (IR7–0) are raised
high, setting the corresponding IRR bit(s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if
appropriate.
3. The CPU acknowledges the INT and responds with an INTA pulse.
4. Upon receiving an INTA from the CPU group, the highest priority
ISR bit is set, and the corresponding IRR bit is reset. The 8259A will
also release a CALL instruction code (11001101) onto the 8-bit Data
Bus through its D7–0 pins.
5. This CALL instruction will initiate two more INTA pulses to be sent
to the 8259A from the CPU group.
6. These two INTA pulses allow the 8259A to release its
preprogrammed subroutine address onto the Data Bus. The lower
8-bit address is released at the first INTA pulse and the higher 8-bit
address is released at the second INTA pulse.
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