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The document discusses timing waveforms for read and write transactions in a CPU-Bus interface, highlighting the use of latches and registers to manage hold times and ensure data integrity despite clock skew. It explains how over-constraining synthesis is necessary to meet setup and hold requirements for both read and write operations. Additionally, it contrasts latch-based and register-based re-timing approaches, noting the advantages of using edge-triggered registers for easier design-for-test implementation.

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Serajeldeen Ghalyoub 201-801-104
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14 views2 pages

New Microsoft Word Document

The document discusses timing waveforms for read and write transactions in a CPU-Bus interface, highlighting the use of latches and registers to manage hold times and ensure data integrity despite clock skew. It explains how over-constraining synthesis is necessary to meet setup and hold requirements for both read and write operations. Additionally, it contrasts latch-based and register-based re-timing approaches, noting the advantages of using edge-triggered registers for easier design-for-test implementation.

Uploaded by

Serajeldeen Ghalyoub 201-801-104
Copyright
© © All Rights Reserved
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The timing waveform for a read transaction is shown in Figure 9-9.

In this
example the CPU clock is twice the frequency of HCLK. The Low-phase input
latches (LphLAT) are transparent when HCLK is low. Input data is guaranteed
by over-con straining synthesis to arrive before the rising edge of HCLK. At
the rising edge of HCLK, the latch captures the input data and holds the data
for half an HCLK cycle. This guarantees that the data to the CPU will meet
setup and hold requirements, even with significant skew on CPUCLK late
relative to HCLK. CPU issues write CPUCLK CPU holds data until here Latch
holds data HCLK Clock Skew OUTPUT LATCH OPEN AMBA WRITE DATA Bus
completes write Figure 9-10 Write Timing for Latch-based Re-timing Figure 9-
10 shows how the output hold times to the SOC interface is managed. The
High-phase HphLAT latches are transparent with HCLK is high. If the CPU
clock is early, then the latch holds the old data on the bus until the write is
complete. If the CPU clock is late, then data will be late arriving on the bus,
so we over constraint the bus write timing in synthesis to guarantee that
writes work correctly even if data is late by our worst case clock skew. Thus
for both read and write, the system level timing interfaces must be over-con
strained to meet the worst case setup paths on inputs and outputs across
the clock domains. The latch methodology assures that the hold times are
managed safely in both directions. An alternative approach to the CPU-Bus
interface using standard rising-edge register is shown in Figure 9-11. To avoid
the complications of latches we run the CPU clock in advance of the bus
interface clock, guaranteeing the hold times from the SOC to the CPU –
providing the timing constraints on the SOC bus system are tightened to
meet earlier timing to the CPU read path. Frequency and Voltage Scaling
Design TCM CACHE (MEMORIES) L-SHIFT CPUCLK CPURESET_N L-SHIFT /
CLAMP L-SHIFT CPU (STD-CELL LOGIC) L-SHIFT L-SHIFT HCLK REG AMBA Bus
Figure 9-11 Register-based Re-timing 135 Dynamic Voltage RAM with
memory retention Dynamic Voltage CPU with power-down VDDRAM VDDCPU
Figure 9-12 shows the write timing for this design. The CPU clock runs early
enough so that it generates write data, the data is available at the input of
REG early enough to meet the setup time requirements of the register. Write
data is sampled by the regis ter at the rising edge of HCLK and held for the
duration of the write transaction. EARLY CPU CLOCK CPUCLK EARLY CPU
OUTPUTS BUS CLOCK HCLK RETIMED BUS OUTPUTS Figure 9-12 Write Timing
for Register-based Re-timing On read timing, we simply rely on the system to
return read data before the CPU clock that occurs just before the rising edge
of HCLK. One advantage of this register-based approach is that it uses all
edge-triggered regis ters, so standard implementation work effectively to
assure correct timing. This makes automated design-for-test straightforward,
but does requires tighter over-con straining of the input paths to the CPU
interface

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