ELE546T

Embedded Systems
Dr. Rohini. P
Department of ECE,
IIITDM Kancheepuram

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Bit-specific addressing
TM4C family implements a flexible way to access port pins
Doesn’t work for all the I/O registers, just the parallel port
data registers
Allows collective access to 1 to 8 bits in a data port
Basically, if we are interested in bit b, the constant is 4*2b
Each possible bit combination has a separate address for
accessing that combination
There are 256 possible bit combinations we might be
interested in accessing, from all of them to none of them
The base addresses for the data ports can be in data manual.

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Bit-specific addressing
For example, assume we are interested in Port A bits 1, 2, and 3
 The base address for Port A is 0x4000.4000, and the constants are 0x0008, 0x0010, and
0x0020
The sum of 0x4000.4000+0x0008+0x0010 +0x0020 is the address 0x4000.4038
If we read from 0x4000.4038 only bits 1, 2, and 3 will be returned
If we write to this address only bits 1, 2, and 3 will be modified

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Switch Interface
Positive logic, external Positive logic, internal
+3.3V +3.3V
TM4C TM4C
in in PA4
PA5
10k PDR=1

Negative logic, external Negative logic, internal

+3.3V
TM4C +3.3V
10k
PUR=1
in in
PA7 PA6
TM4C

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

LED interfaces
Positive logic, low current Positive logic, high current
high +5V
Out TM4C 7405 R 10mA
R 2mA or 7406
TM4C +5V LED
LED high
Out 0.5V
PF2

Negative logic, low current Negative logic, high current

+5V
3.3 V 10mA
TM4C TM4C
R
R 7407
2mA +5V LED
LED low
Out 0.5V
Out
low

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

 Phase-Lock-Loop

TM4C has different clock sources:

Precision Internal Oscillator (PIOSC) : 16 MHz.

Main Oscillator (MOSC) : It can use an external clock source or an external crystal.

Low-Frequency Internal Oscillator (LFIOSC) : An on-chip internal 30 kHz Oscillator used for

Deep-Sleep power-saving modes.

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

 Phase-Lock-Loop

 Internal oscillator requires minimal power but is imprecise

 External crystal provides stable bus clock
 TM4C123 is equipped with 16.000 MHz crystal and bus clock can be set to a
maximum of 80 MHz

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
Registers used

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

To activate a microcontroller with a 16 MHz main oscillator to run at 80 MHz.

Use RCC2 because it provides for more options.

1. Set BYPASS2 (bit 11) - At this point the PLL is bypassed - no system clock divider

2. Specify the crystal frequency in the four XTAL bits using the code - OSCSRC2 bits are cleared to select the main
oscillator as the oscillator clock source

3. Clear PWRDN2 (bit 13) to activate the PLL

4. Configure and enable the clock divider using the 7-bit SYSDIV2 field. If the 7-bit SYSDIV2 is n, then the clock
will be divided by n+1 (To get 80 MHz from 400 MHz PLL - divide by 5 - place a 4 into the SYSDIV2 field)

5. Wait for the PLL to stabilize by waiting for PLLRIS (bit 6) in the SYSCTL_RIS_R to become high.

6. Connect the PLL by clearing the BYPASS2 bit.

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

 SysTick Timer

 Timer/Counter operation
 24-bit counter decrements at bus clock
 With 80 MHz bus clock, decrements every 12.5 ns

 Counting is from n → 0
 Assume RELOAD= n n=0xFFFFFF

 CURRENT is a modulo n+1 counter

 next_value = (current_value-1) mod (n+1)

 Sequence: n,n-1,n-2,n-3… 2,1,0,n,n-1…

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

SysTick Timer
Address 31-24 23-17 16 15-3 2 1 0 Name
$E000E010 0 0 COUNT 0 CLK_SRC INTEN ENABLE NVIC_ST_CTRL_R
$E000E014 0 24-bit RELOAD value NVIC_ST_RELOAD_R
$E000E018 0 24-bit CURRENT value of SysTick counter NVIC_ST_CURRENT_R

Initialization (4 steps)
Step1: Clear ENABLE to stop counter
Step2: Specify the RELOAD value
Step3: Clear the counter via NVIC_ST_CURRENT_R
Step4: Set NVIC_ST_CTRL_R
CLK_SRC = 1 (bus clock is the only option)
INTEN = 0 for no interrupts
ENABLE = 0 to enable

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

SysTick Timer in C
#define NVIC_ST_CTRL_R(*((volatile uint32_t *)0xE000E010))
#define NVIC_ST_RELOAD_R(*((volatile uint32_t *)0xE000E014))
#define NVIC_ST_CURRENT_R(*((volatile uint32_t *)0xE000E018))

void SysTick_Init(void){
NVIC_ST_CTRL_R = 0; // 1) disable SysTick during setup
NVIC_ST_RELOAD_R = 0x00FFFFFF; // 2) maximum reload value
NVIC_ST_CURRENT_R = 0; // 3) any write to CURRENT clears it
NVIC_ST_CTRL_R = 0x00000005; // 4) enable SysTick with core clock
}
// The delay parameter is in units of the 80 MHz core clock(12.5 ns)
void SysTick_Wait(uint32_t delay){
NVIC_ST_RELOAD_R = delay-1; // number of counts
NVIC_ST_CURRENT_R = 0; // any value written to CURRENT clears
while((NVIC_ST_CTRL_R&0x00010000)==0){ // wait for flag
}
}
// Call this routine to wait for delay1*10ms
void SysTick_Wait10ms(uint32_t delay1){
unsigned long i;
for(i=0; i<delay; i++){
SysTick_Wait(800000); // wait 10ms
}t
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
 Finite State Machine (FSM)

 What is a finite state machine?

 Inputs (sensors)
 Outputs (actuators)
 Controller
 State graph ↔ State table

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

 Finite State Machine (FSM)
 Moore FSM
 output value depends only on the current state,
 inputs affect the state transitions
 significance is being in a state
 Input: when to change state
 Output: definition of being in that state

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

 Traffic Light FSM

PE1=0, PE0=0 means no cars exist on either road

PE1=0, PE0=1 means there are cars on the East road
PE1=1, PE0=0 means there are cars on the North road
PE1=1, PE0=1 means there are cars on both roads

• Use Moore when the output is needed to be IN the state

goN, PB5-0 = 100001 makes it green on North and red on East
waitN, PB5-0 = 100010 makes it yellow on North and red on East
goE, PB5-0 = 001100 makes it red on North and green on East
waitE, PB5-0 = 010100 makes it red on North and yellow on East

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

 Traffic Light FSM

State \ Input 00 01 10 11
goN (100001,30) goN waitN goN waitN
waitN (100010,5) goE goE goE goE
goE (001100,30) goE goE waitE waitE
waitE (010100,5) goN goN goN goN

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

#define SENSOR (*((volatile uint32_t *)0x4002400C)) int main(void){ volatile uint32_t delay;
#define LIGHT (*((volatile uint32_t *)0x400050FC))
PLL_Init(); // 80 MHz,
// Linked data structure
struct State { SysTick_Init();
uint32_t Out; SYSCTL_RCGCGPIO_R |= 0x12; // B E
uint32_t Time; delay = SYSCTL_RCGCGPIO_R; // no need to unlock
uint32_t Next[4];};
GPIO_PORTE_DIR_R &= ~0x03; // inputs on PE1-0
typedef const struct State State_t;
#define goN 0 GPIO_PORTE_DEN_R |= 0x03; // enable digital on PE1-0
#define waitN 1 GPIO_PORTB_DIR_R |= 0x3F; // outputs on PB5-0
#define goE 2 GPIO_PORTB_DEN_R |= 0x3F; // enable digital on PB5-0
#define waitE 3
S = goN;
State_t FSM[4]={
{0x21,3000,{goN,waitN,goN,waitN}}, while(1){
{0x22, 500,{goE,goE,goE,goE}}, LIGHT = FSM[S].Out; // set lights
{0x0C,3000,{goE,goE,waitE,waitE}}, SysTick_Wait10ms(FSM[S].Time);
{0x14, 500,{goN,goN,goN,goN}}};
Input = SENSOR; // read sensors
uint32_t S; // index to the current state
uint32_t Input; S = FSM[S].Next[Input];
}
}
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
 Stepper motor
 A bipolar stepper motor has two coils on the stator

 There is always current flowing through both coils.

 When current flows through both coils, the motor does not spin

 To move a bipolar stepper, we reverse the direction of current through

one (not both) of the coils

 To move it again we reverse the direction of current in the other coil

 To make the current go up, the microcontroller outputs a binary 01 to

the interface.

 To make the current go down, it outputs a binary 10

 Since there are 2 coils, four outputs will be required (e.g.,

01012 means up/up)
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
I/O Synchronization
 Performance Measure - goodness of the system

 Latency - time between when the I/O device indicated service is required and the time when service is initiated
 Includes hardware delays in the digital hardware plus computer software delays.

 For an input device, software latency - time between new input data ready and the software reading the data

 For an output device, latency - delay from output device idle and the software giving the device new data to output.

 A real-time system is one that can guarantee a worst case latency - the software response time is small and bounded - to satisfy
overall specification of the system, such as no lost data.

 Throughput or bandwidth is the maximum data flow in bytes/second that can be processed by the system

 Priority determines the order of service when two or more requests are made simultaneously
 Priority also determines if a high-priority request should be allowed to suspend a low priority request that is currently being
processed

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Synchronization Mechanisms

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Synchronization Mechanisms

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

FIFO
Store or buffer data in a first in first out (FIFO) queue, while passing the data from one
module to another.
Buffer separates the generation of data from the consumption of data-very efficient
Can handle situations where there is an increase or decrease in the rates at which data is
produced or consumed
Other names - bounded buffer, producer-consumer, and buffered I/O
Data are entered into the FIFO as they arrive - call Put to store data in the FIFO
Data are removed as they leave - call Get to remove data from the FIFO
Maintains the order of the data, as it passes through the buffer

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Serial Communication
Serial transmission involves sending one bit at a time, such that the data is spread out
over time
The total number of bits transmitted per second is called the baud rate
The reciprocal of the baud rate is the bit time, which is the time to send one bit
frame is the smallest complete unit of serial transmission
bandwidth - the amount of data or useful information transmitted per second
bandwidth of the serial channel (in bytes/second) ?

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Asynchronous serial Communication
 Transmitter - 16-element FIFO and a 10-bit shift register

 To output data using the UART, the software will first check to make sure the transmit FIFO is not full (it will wait if TXFF is 1) and then
write to the transmit data register (UART0_DR_R )

 Shifted out in order - start, b0, b1, b2, b3, b4, b5, b6, b7, and then stop

 Transmit data register is write only

 Even though the transmit data register is at the same address as the receive data register, the transmit and receive data registers are two
separate registers.

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Asynchronous serial Communication

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
Initialization steps
 To activate a UART, turn on the UART clock in the RCGCUART register

 Turn on the clock for the digital port in the RCGCGPIO register.

 Enable the transmit and receive pins as digital signals.

 The alternative function for these pins must also be selected. In particular we set bits in both the AFSEL and PCTL registers.

 The OE, BE, PE, and FE are error flags associated with the receiver.

 You can see these flags in two places: associated with each data byte in UART0_DR_R or as a separate error register in UART0_RSR_R.

 The overrun error (OE) is set if data has been lost because the input driver latency is too long.

 BE is a break error, meaning the other device has sent a break.

 PE is a parity error

 The framing error (FE) will get set if the baud rates do not match.

 The software can clear these four error flags by writing any value to UART0_RSR_R.

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
The status of the two FIFOs can be seen in the UART0_FR_R register.

The UART0_CTL_R control register contains the bits that turn on the UART.

TXE is the Transmitter Enable bit,

RXE is the Receiver Enable bit.

We set TXE, RXE, and UARTEN equal to 1 in order to activate the UART device.

However, we should clear UARTEN during the initialization sequence.

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
 // Wait for new input, then return ASCII code
// Assumes a 80 MHz bus clock, creates 115200 baud rate
char UART_InChar(void){
void UART_Init(void){ // should be called only once

SYSCTL_RCGCUART_R |= 0x00000002; // activate UART1 while((UART0_FR_R&0x0010) != 0); // wait until RXFE is 0

SYSCTL_RCGCGPIO_R |= 0x00000004; // activate port C return((char)(UART0_DR_R&0xFF));

UART1_CTL_R &= ~0x00000001; // disable UART }

UART1_IBRD_R = 43; // IBRD = int(80,000,000/(16*115,200)) = int(43.40278)
// Wait for buffer to be not full, then output
UART1_FBRD_R = 26; // FBRD = round(0.40278 * 64) = 26
void UART_OutChar(char data){
UART1_LCRH_R = 0x00000070; // 8 bit, no parity bits, one stop, FIFOs
while((UART0_FR_R&0x0020) != 0); // wait until TXFF is 0
UART1_CTL_R |= 0x00000001; // enable UART

GPIO_PORTC_AFSEL_R |= 0x30; // enable alt funct on PC5-4 UART0_DR_R = data;

GPIO_PORTC_DEN_R |= 0x30; // configure PC5-4 as UART1 }

GPIO_PORTC_PCTL_R = (GPIO_PORTC_PCTL_R&0xFF00FFFF)+0x00220000;

GPIO_PORTC_AMSEL_R &= ~0x30; // disable analog on PC5-4

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Synchronous Serial Interface
SSI – master/ slave

(1 master + 1 slave) or (1 master + multiple slaves)

With multiple slaves – ring or star configuration

Master initiates all data communication

Two devices communicating with synchronous serial interfaces (SSI) operate from the same clock
(synchronized)

With a SSI protocol, the clock signal is included in the interface cable between devices

The master device creates the clock, and the slave device(s) uses the clock to latch the data (in or out.)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Synchronous Serial Interface
The SSI protocol includes four I/O lines

The slave select SSI0Fss - control signal from master to slave signal signifying the channel is active

The second line, SCK, is a 50% duty cycle clock generated by the master

The SSI0Tx (master out slave in, MOSI) is a data line driven by the master and received by the slave

 The SSI0Rx (master in slave out, MISO) is a data line driven by the slave and received by the master

In order to work properly, the transmitting device uses one edge of the clock to change its output, and
the receiving device uses the other edge to accept the data

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
Interrupts
Automatic transfer of software execution in response to a hardware event
Hardware event – trigger - Busy to ready transition – raise a trigger flag
Thread – path of action of a software as it executes
Interrupt service routine – background thread
Created by Hardware interrupt request – killed when ISR returns from the interrupt
New thread created for each interrupt- local variable and registers used in the ISR are
unique and separate
Multi threaded system – many threads – co-operate, communicate and synchronize with
each other

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Interrupts
To Arm/ disarm a device – enable the source of interrupts

Each trigger has a separate arm bit

Arms a trigger – if interested in receiving the interrupt from that source

Enable/ disable interrupts – postponing to a later time

Arm cortex – 1 enable bit for entire interrupt system

Disable if it is not convenient to receive interrupt at that time

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Registers
The special-purpose mask register, PRIMASK

BASEPRI = Base Priority Mask Register

Nonzero = defines the base priority for exception processing.

The processor does not process any exception with a priority value greater than or equal to
BASEPRI
Interrupt Program Status Register

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Conditions for an interrupt to be generated
Device Arm

NVIC enable

Global enable – I bit must be 0

Level of Priority

Trigger – Hardware trigger flag – RIS register

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Context switch
An Interrupt causes the following events
Current instruction execution is completed

Execution of the current program is suspended

Pushes 8 register on stack – R0, R1, R2, R3, R12, LR, PC, PSR --- R0 on top

LR – set with 0xFFFFFFF9

IPSR – set to interrupt number being processed

PC is loaded with the address of the ISR

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Interthread Communication and Synchronization

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Interthread Communication and Synchronization

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Interthread Communication and Synchronization

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])
Nested Vectored Interrupt Controller (NVIC)

Hardware unit that coordinates among interrupts from multiple

sources
Define priority level of each interrupt source (NVIC_PRIx_R registers)
Separate enable flag for each interrupt source (NVIC_EN0_R,
NVIC_EN1_R)

Interrupt does not set I bit

Higher priority interrupts can interrupt lower priority ones

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

NVIC Interrupt Enable Registers
Enable registers –
NVIC_EN0_R to NVIC_EN4_R
Each 32-bit register has a single enable bit for a particular device

NVIC_EN0_R control the IRQ numbers 0 to 31 (interrupt numbers 16 – 47)

NVIC_EN1_R control the IRQ numbers 32 to 47 (interrupt numbers 48 – 63)

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

NVIC Priority Registers
High order three bits of each byte define priority

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Registers
GPIO Register Tivaware Name Each Bit Value (Lowest 8-Bit) and Each Pin Function

Interrupt sense register

Determines level or edge triggered
GPIOIS GPIO_PORTx_IS_R
0: Detect an edge (edge-sensitive) on the pin,
1: Detect a level (level-sensitive) on the pin.

0: Interrupt is controlled by GPIOIEV,

GPIOIBE GPIO_PORTx_IBE_R
1: Both edges on the corresponding pin trigger an interrupt

GPIO Interrupt Event Register

Determines the detecting edges or levels.
GPIOIEV GPIO_PORTx_IEV_R
0: A falling edge or a LOW level,
1: A rising edge or a HIGH level triggers an interrupt

GPIO Interrupt Mask Register

Masks (disables) or unmask (enable) an interrupt.
GPIOIM GPIO_PORTx_IM_R
0: Interrupt is masked (disabled),
1: Interrupt is unmasked (enabled).

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

 GPIOIS GPIOIEV
(interrupt sense) (Interrupt Event)
0 0 Falling edge
0 1 Rising edge
1 0 Low level
1 1 High level

DIR AFSEL PTCL IS IBE IEV IME Port mode

0 0 0000 0 0 0 0 Input, falling edge trigger, busy wait

0 0 0000 0 0 1 0 Input, rising edge trigger, busy wait

0 0 0000 0 1 - 0 Input, both edges trigger, busy wait

0 0 0000 0 0 0 1 Input, falling edge trigger, interrupt
0 0 0000 0 0 1 1 Input, rising edge trigger, interrupt
0 0 0000 0 1 - 1 Input, both edges trigger, interrupt

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])

Registers
GPIO Register Tivaware Name Each Bit Value (Lowest 8-Bit) and Each Pin Function

GPIO Raw Interrupt Status Register

Indicates the raw interrupt status for a pin.
0: No interrupt occurred on the pin,
GPIORIS GPIO_PORTx_RIS_R 1: An interrupt is occurred on the pin.
For the edge-triggered interrupts,
write a 1 to the corresponding pin in ICR_R to clear that interrupt.
For level-triggered interrupt, no action is needed.

GPIO Masked Interrupt Status Register

Indicates the state of the interrupt.
0: An interrupt condition on the corresponding pin is masked or has not
GPIOMIS GPIO_PORTx_MIS_R
occurred.
1: An interrupt condition on the corresponding pin has triggered an interrupt
to the interrupt controller.

GPIO Interrupt Clear Register

Clears an edge-triggered interrupt.
GPIOICR GPIO_PORTx_ICR_R
0: No action,
1: The corresponded edge-triggered interrupt is cleared.

Dr. Rohini. P, Department of ECE, IIITDM Kancheepuram. (Email: [email protected])