Chapter 3

Gate-Level Minimization

Outline
 The Map Method
 Four-Variable Map
 Five-Variable Map
 Product-of-Sum Simplification
 Don’t Care Conditions
 NAND and NOR Implementation
 Other Two-Level Implementations
 Exclusive-OR Function
 Hardware Description Language (HDL)

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 The Map Method
 Gate-level minimization refers to the design task of finding
an optimal gate-level implementation of Boolean functions
describing a digital circuit.
 The complexity of the digital logic gates has close relation
with the complexity of the algebraic expression.
 The map method provides a straightforward logic
minimization. Maurice Karnaugh
 Logic minimization
– Algebraic approaches: lack specific rules
– the Karnaugh map (K-map)
 a simple straight forward procedure
 a pictorial form of a truth table
 applicable if the # of variables < 7

The Map Method

 A diagram made up of squares
– each square represents one minterm
 Boolean function
– sum of products (minterms) and product of sums
(maxterms) are two basic standard algebraic expressions
– The simplified algebraic expression is one with a
minimum number of terms and a minimum number of
literals
– The simplified expression may not be unique

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 Two-Variable Map
 A two-variable map
– Four minterms
– x' = row 0; x = row 1
– y' = column 0;
y = column 1
– a truth table in square
diagram
– F = xy = (m3)
– F = x'y + xy' + xy
= (m1 , m2 , m3)
= x+ y

Three-Variable Map
 A three-variable map
– Eight minterms
– The Gray code sequence
– Any two adjacent squares
in the map differ by only
one variable
 primed in one square and
unprimed in the other
 Any combination of 2
adjacent squares reduces to
an expression with 2 literals.
– Example:
 m5 and m7 can be simplified
 m5 + m7 = xy'z + xyz
= xz (y' + y) = xz 6
 Three-Variable Map
 Example:
– m0 and m2 (m4 and m6) are adjacent
– m0 + m2 = x'y'z' + x'yz' = x'z' (y' + y) = x'z'
– m4 + m6 = xy'z' + xyz' = xz' (y' + y) = xz'

Examples
 Example 3-1
– F(x, y, z) = (2, 3, 4, 5)
– F = x'y + xy'
= x♁y

 Example 3-2
– F(x, y, z) = (3, 4, 6, 7)
= yz + xz'

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 Four Adjacent Squares
– Any combination of 4 adjacent squares reduces to an
expression with only one literal.
– m0 + m2 + m4 + m6 = x'y'z' + x'yz' + xy'z' + xyz'
= x'z'(y' + y) + xz'(y' + y)
= x'z' + xz' = (x' + x)z' = z'
– m1 + m3 + m5 + m7 = x'y'z + x'yz + xy'z + xyz
= x'z(y' + y) + xz(y' + y) = x'z + xz = z

Example 3-3
– F(x, y, z) = (0, 2, 4, 5, 6) = m0 + m2 + m4 + m5 + m6
– F = z' + xy'

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 Example 3-4
– F = A'C + A'B + AB'C + BC 1. By algebraic approach
a) express it in sum of minterms 2. By truth table
3. By graphic method
b) find the minimal sum of products
expression from maximam to minimum squares

F = A'B + C

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Four-Variable Map
 Construction of the map:
– consists of 16 minterms
– checks the combinations of 2, 4, 8, and 16 adjacent
squares.
– The rows and columns are numbered in a Gray code
sequence, with only one digit changing value between
two adjacent rows or columns.

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 Example 3-5
– F(w, x, y, z) = (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
– F = y' + w'z' + xz'

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Example 3-6
– F = ABC + BCD + ABCD + ABC
– Simplified: F = B D + B C + A CD

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 Prime Implicants
 We have to ensure:
– All the minterms are covered
– Minimize the number of terms
– No redundant terms (i.e., minterms already covered by other terms)
 A prime implicant: a product term obtained by combining
the maximum possible number of adjacent squares
(combining all possible maximum numbers of squares)
 Essential prime implicant: a minterm that is covered by only
one prime implicant that prime implicant is said to be
essential
 The simplified expression is obtained from the logical sum
of:
– All the essential prime implicants and
– Other prime implicants that need to cover other remaining minterms
that are not covered by essential prime implicants. 15

Essential Prime Implicants

 Example: F(A, B, C, D) = (0, 2, 5, 7, 8, 10, 13, 15)

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 Prime Implicants
 Example: F(A, B, C, D) = (0, 2, 3, 5, 7, 8, 9, 10, 11, 13,
15)
– the simplified expression may not be unique
– F = BD + B'D' + CD + AD = BD + B'D' + CD + AB
= BD + B'D' + B'C + AD = BD + B'D' + B'C + AB'

Essential Prime Implicants:

BD, B'D'
Prime Implicants:
CD, AD, B'C, AB

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Five-Variable Map
 Map for more than four variables becomes
complicated
– five-variable map: two four-variable maps (one on the
top of the other)

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 Example 3-7
– F = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)
– F = A'B'E' + BD'E + ACE

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Another Map for Example 3-7

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 The K-Map Conclusion
 The relationship between the number of adjacent
squares and the number of literals in the term:
Number of
Number of Literals in a Term in
Adjacent
an n -variable map
Squares
K 2k n=2 n=3 n=4 n=5
0 1 2 3 4 5
1 2 1 2 3 4
2 4 0 1 2 3
3 8 0 1 2
4 16 0 1
5 32 0
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Product of Sums Simplification

 Approach # 1: The product of sums simplification is
based on the generalized DeMorgan’s theorem.
– (0’s in the K-map): Simplified F' in the form of sum of
products.
– (1’s in the K-map): Apply DeMorgan's theorem F = (F')'
– F': sum of products  F: product of sums
 Approach # 2: Conversion b/w SOP and POS
– combinations of maxterms (it was minterms)
– M0M1 = (A + B + C + D)(A + B + C + D') CD
AB 00 01 11 10
= (A + B + C)(D + D')
00 M0 M1 M3 M2
=A+B+C
01 M4 M5 M7 M6
11 M12 M13 M15 M14
10 M8 M9 M11 M10 22
 Example 3-8
– Simplified the function: F = (0, 1, 2, 5, 8, 9, 10)
– a) Sum of products:
F = B’D’+B’C’+A’C’D

– b) Product of sums
– F' = AB+CD+BD'
– Apply DeMorgan's
theorem;
F = (A'+B')(C'+D')(B'+D)
– or think in terms of maxterms
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Gate Implementation of the

Function of Example 3-8

Two-Level Logic Implementation!!

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 Don't-Care Conditions
 The value of a function is not specified for certain
combinations of variables
– BCD: 1010 ~ 1111 are don't care terms
 The don't care conditions can be utilized in logic
minimization
– Because either 0 or 1 can be implemented; the logic
optimization is more flexible for simplified gates.
 Example 3-9
– Boolean function: F(w, x, y, z) = (1, 3, 7, 11, 15)
– Don’t care condition: d(w, x, y, z) = (0, 2, 5)
– F = yz + w'x'; F = yz + w'z
– F = (0,1,2,3,7,11,15) ; F = (1,3,5,7,11,15)
– either expression is acceptable
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Example of Don’t-Care Conditions

w/o don’t care conditions: F = yz + w’x’z

In terms of POS: F = z(w’ + y) 26
NAND and NOR Implementation
 NAND ( + logic) and NOR (– logic) gates are easier to
fabricate with electronic components than AND and OR
gates.
 NAND gate is a universal gate because any operation can
be implemented by it.

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Equivalent NAND Gates

 The AND-invert and Invert-OR are equivalent,
following the DeMorgan’s theorem.
 Two graphic symbols are for a NAND gate

 The conversion between AND-Invert and Invert-OR

makes the NAND implementation.

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 NAND-NAND Implementation
 Two-level NAND implementation procedure
– 1. Simplify the function in the form of sum of products.
– 2. Draw a NAND gate for each product term. The inputs
to each NAND gate are the literals of the term forming a
group of 1st level gate.
– 3. Draw gates using AND-Invert or the Invert-OR in the
second level. (Note: keep function by DeMorgan’s
theorem)
– 4. Single literal must be complemented for first or
second level.

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Example
 F = AB + CD
– Three ways to implement F

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 Two-Level NAND Implementation
 Two-level logic
 NAND-NAND = sum of products
 Example: F = AB + CD + E
 F = ((AB)' (CD)' E')' = AB + CD + E

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Example 3-10
 F(x, y, z) = (1, 2, 3, 4, 5, 7) = xy’ + x’y + z

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 Multilevel NAND Circuits
 Multilevel NAND circuit implementation procedure
– 1. Convert all AND gates to NAND gates with AND-Invert
graphic symbols
– 2. Convert all OR gates to NAND gates with Invert-OR
graphic symbols
– 3. Check all the bubbles (Inverter) in the diagram and
insert possible inverter to keep the original function.

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Multilevel NAND Circuits

 Boolean function implementation
– AND-OR logic  NAND-NAND logic
 AND  NAND + inverter
 OR: inverter + OR = NAND
Implementing F = A(CD + B) + BC

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 NOR Implementation
 NOR function is the dual of NAND function
 The NOR gate is also universal

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Two graphic symbols for a NOR gate

 Boolean-function implementation
– OR  NOR + INV
– AND: INV + AND = NOR

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Example: Implementation with NOR
Gate
F = (A + B)(C + D)E

F = (AB + AB)(C + D)

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Other Two-level Implementations

 Wired logic
– a wire connection between the outputs of two
gates (Not a physical two-level logic)
– open-collector TTL NAND gates: wired-AND logic
– the NOR output of ECL gates: wired-OR logic
AND-OR-INVERT function
OR-AND-INVERT function

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 Degenerate Forms
 AND/NAND/OR/NOR have 16 possible
combinations of two-level forms
– eight of them: degenerate forms  a single operation
 AND-AND  AND
 OR-OR  OR
 AND-NAND  NAND
 OR-NOR  NOR
 NAND-NOR  AND
 NOR-NAND  OR
 NAND-OR  NAND
 NOR-AND  NOR

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Nondegenerate Forms

 AND-OR  standard sum-of-products

 NAND-NAND  standard sum-of-products
 OR-AND  standard product-of-sums
 NOR-NOR  standard product-of-sums
 NAND-AND/AND-NOR  AND-OR-INVERT (AOI)
circuit (complement of sum-of-products)
 OR-NAND/NOR-OR  OR-AND-INVERT (OAI)
circuit (complement of product-of-sums)

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AND-OR- Invert Implementation
 AND-OR-INVERT (AOI) Implementation
– NAND-AND = AND-NOR = AOI
– F = (AB + CD + E)'
– F' = AB + CD + E (sum of products)

 Usage
– Combining 0’s in K-map to simplify F' in sum-of-products
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Example
 Example 3-11: Implement the function F using AOI
two-level form
– F' = x'y + xy' + z
(F': sum of products)
– F = (x'y + xy' + z)'
(F: AOI implementation)

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 OR-AND- INVERT (OAI )
Implementation
 OR-AND-INVERT (OAI) Implementation
– OR-NAND = NOR-OR = OAI
– F = ((A + B)(C + D)E)'
– F' = (A + B)(C + D)E (product of sums)

 Usage
– Combining 1’s in K-map to simplify F' in product-of-sums (OR-AND)
and then inverting the result to get F in (OAI). (hint: DeMorgan’s
theorem) 45

Example
 Example 3-11: Implement the function F using OAI
two-level form
– F = x'y'z' + xyz'
(F: sum of products)
– F' = (x + y + z)(x' + y' + z)
(F': product of sums)
– F = ((x + y + z)(x' + y' + z))'
(F: OAI)

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 Tabular Summary

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Exclusive-OR Function
 Exclusive-OR (XOR)  Some identities
– x y = xy' + x'y – x 0 = x
 Exclusive-NOR (XNOR) – x 1 = x'
– (x y)' = xy + x'y' – x x = 0
– x x' = 1
– x y' = (x y)'
– x' y = (x y)'
 Commutative and associative
– A B = B A
– (A B) C = (AB' + A'B)C' + (AB + A'B')C
= AB'C' + A'BC' + ABC + A'B'C
= A(BC + B’C’) + A'(BC' + B’C) = A(B C)’ + A'(B C)
= A  (B C) = A B C 48
 XOR Implementations
 Implementations
– (x' + y')x + (x' + y')y = xy' + x'y = x y

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Odd / Even Function

 A  B  C = (AB' + A'B)C' + (AB + A'B')C
= AB'C' + A'BC' + ABC + A'B'C
= (1, 2, 4, 7)
 an odd number of 1's

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 XOR Functions
 Logic Diagrams of Odd/Even Functions

 Four-variable Exclusive-OR function

– A B C D = (AB’ + A’B) (CD’ + C’D)
= (AB' + A'B)(CD + C'D') + (AB + A'B')(CD' + C'D)

Odd Even

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Parity Generation and Checking

 Parity Generation (at Tx) and Parity Checker (at Rx)
– a parity bit: P = x y z
– parity check: C = x y z P
 C = 1: an odd number of data bit error

 C = 0: correct or an even # of data bit error

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 Parity Generation and Checking
 Truth Table (in the transmitter or storage input)

Three Bits Message Parity Bit

x y z P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
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Parity Generation and Checking

 Truth Table (in the receiver and storage output)

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Hardware Description Language (HDL)
 Describe the design of digital systems in a textual
form (can be read by both humans and computers)
– Design Entry: hardware structure
– Logic Simulation: function/behavior simulations and
verifications
– Logic Synthesis: Process of deriving a list of physical
components and their interconncets (netlist)
– Timing Verification: speed test
– Fault Simulation: identifying input stimuli to reveal the
difference b/w faulty circuit and fault-free circuit
 VHDL (by DoD) and Verilog HDL (by Cadence, 益華
電腦)
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EDA Tools

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A Top-Down Design Flow
Specification Define input and output

RTL design and RTL: Register Transfer

Logic Simulation Level (Chap. 8)

Logic Synthesis

Gate Level Simulation

ASIC Layout FPGA Implementation

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